The present disclosure relates to a measurement mark, a semiconductor structure, a measurement method and device, and a storage medium. The measurement mark is provided on a semiconductor structure, the semiconductor structure including a substrate. The measurement mark is applied to an after etching inspection process. The measurement mark includes a first mark layer and a second mark layer, the first mark layer and the second mark layer being stacked. A projection contour of the first mark layer on the substrate coincides with a projection contour of the second mark layer on the substrate. The measurement mark includes a first mark group located on the first mark layer and a second mark group located on the second mark layer.

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a plurality of chip connection bumps between the first semiconductor chip and the second semiconductor chip, a protective insulating layer between the first semiconductor chip and the second semiconductor chip, the protective insulating layer contacting the plurality of chip connection bumps, and a first dummy conductive structure at a bottom surface of the second semiconductor chip. When viewed in a plan view, the first dummy conductive structure surrounds an outer boundary of a region where the plurality of chip connection bumps are disposed. The bottom surface of the second semiconductor chip faces the first semiconductor chip. The first dummy conductive structure includes a plurality of dummy patterns separated from each other, and the plurality of dummy patterns are arranged along an edge of the second semiconductor chip.

A display device includes a display panel including a non-display area in which a panel pad is disposed, and a pad portion which contacts the non-display area of the display panel, where the pad portion includes an alignment mark overlapping the panel pad, the panel pad includes a first vertical portion and a second vertical portion spaced apart from each other in a first direction, a first horizontal portion connected to the first vertical portion, and a second horizontal portion connected to the second vertical portion, and the first horizontal portion and the second horizontal portion are spaced apart from each other in a second direction crossing the first direction.

A wiring structure includes an upper conductive structure, a lower conductive structure, an intermediate layer and at least one through via. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The through via extends through the upper conductive structure, the intermediate layer and the lower conductive structure.

A non-volatile memory device and a non-volatile memory system comprising the same are provided. The non-volatile memory device includes a first stack in which a first conductive pattern and a first dielectric layer are alternately stacked in a first direction on a substrate, a second stack in which a second conductive pattern and a second dielectric layer are alternately stacked in the first direction on the first stack opposite the substrate, a first monitoring channel structure that penetrates the first stack in the first direction, and a second monitoring channel structure that penetrates the second stack in the first direction and is =on the first monitoring channel structure. A width of a top of the first monitoring channel structure opposite the substrate is smaller than a width of a bottom of the second monitoring channel structure adjacent the top of the first monitoring channel structure.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.