Provided is a package structure and an antenna structure. The package structure includes a die; a first encapsulant, laterally encapsulating the die; a first redistribution structure, disposed on the first encapsulant and the die; a second encapsulant, disposed on the first redistribution structure; an antenna pattern, embedded in the second encapsulant and electrically connected to the first redistribution structure; and a dielectric layer, covering the antenna pattern, wherein an upper surface of the second encapsulant is exposed by the dielectric layer, and a laser mark is formed within the upper surface of the second encapsulant.

The present disclosure provides improved approaches for marking and individual tracking of solar cells. These approaches can be used to identify key manufacturing process steps requiring optimization and/or significant factors extending solar cell lifetime. The approaches described herein for marking and individual tracking of solar cells avoid or greatly minimize any negative impact on solar cell performance while improving quality control of solar cells across multiple manufacturing steps and throughout the entire solar cell lifecycle. Embodiments described herein include a solar cell comprising a substrate having a front side and a back side. The substrate comprises at least one diffusion region of a first polarity. A first set of conductive conduits in the first set is electrically coupled to at least one active diffusion region of a first polarity. The solar cell further comprises a marking above an inactive region of the substrate. The marking can provide information about a particular cell which can be read or scanned during cell manufacturing and/or in the field during the operational life of the cell.

An embodiment of the present invention is an identification circuit for generating an identification number (ID). The identification circuit includes a plurality of identification cells each comprising a latch having a first output and a second output that are opposite to each other. The first output and the second output are a function of process variations of the identification circuit. A first buffer and a second buffer are provided on both sides of the latch and connected to the first output and the second output of the latch, respectively.

It is an object of the present invention to provide a film for semiconductor back surface having reworkability, and an application of the film. A film for semiconductor back surface has: an adhering strength at 70° C. of 7 N/10 mm or less to a wafer before the film is thermally cured; and a rupture elongation at 25° C. of 700% or less. The film for semiconductor back surface preferably has a degree of swelling due to ethanol of 1% by weight or more. The film for semiconductor back surface preferably contains an acrylic resin.

A substrate includes a ceramic layer, a metal layer fixed in a planar manner on a surface side of the ceramic layer and a cutout arranged in an edge region of the metal layer. The cutout in the edge region codes information. A multiple substrate having a plurality of these substrates is also provided, as is a method for producing the substrate.

A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.

A semiconductor device includes a semiconductor substrate, an effective region formed as a conductive section on the semiconductor substrate, an ineffective region formed as a non-conductive section on the semiconductor substrate, a wiring metal formed in the effective region, a metal section provided on an upper surface of the wiring metal and exposed to an outside, an identifying mark provided on the upper surface of the wiring metal and exposed to the outside, the identifying mark being spaced apart from the metal section, and an insulating body provided on the upper surface of the wiring metal and exposed to the outside, the insulating body being adjacent to the metal section and the identifying mark.

Multi-component modules (MCMs) including configurable electromagnetic interference (EMI) shield structures, and related methods are disclosed. An EMI shield enclosing an IC or another electrical component in an MCM can protect other components within the MCM from EMI generated by the enclosed component. The EMI shield also protects the enclosed component from the EMI generated by other electrical components. An EMI shield with side-wall structures, in which vertical conductors supported by a wall medium electrically couple a lid of the EMI shield to a ground layer in a substrate, provides configurable EMI protection in an MCM. The EMI shield may also be employed to increase heat dissipation. The side-wall structures of the EMI shield are disposed on one or more sides of an electrical component and are configurable to provide a desired level of EMI isolation.

A semiconductor package is provided. The semiconductor package may include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips, a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips, a reinforcement layer disposed on the chip stack, and a molding layer surrounding side surfaces of the chip stack and the bonding wires and contacting side surfaces of the reinforcement layer. The reinforcement layer may include a lower layer including an adhesive, an intermediate layer disposed on the lower layer, and an upper layer disposed on the intermediate layer. The intermediate layer may have elongation in a range of 5% to 70%. The upper layer may have elongation less than 5%.

A method of manufacturing a semiconductor package includes the following steps. A backside redistribution structure is formed, wherein the backside redistribution structure comprises a first dielectric layer, and a redistribution metal layer over the first dielectric layer and comprising a dummy pattern. A semiconductor device is provided over the backside redistribution structure, wherein an active surface of the semiconductor device faces away from the backside redistribution structure, the semiconductor device is electrically insulated from the dummy pattern and overlapped with the dummy pattern from a top view of the semiconductor package. A front side redistribution structure is formed over the semiconductor device, wherein the front side redistribution structure is electrically connected to the semiconductor device. A patterning process is performed on the first dielectric layer to form a marking pattern opening exposing a part of the dummy pattern.