A method of forming a charge pattern on a microchip includes depositing a first material on an insulator surface of the microchip, depositing a material having capability of forming a self-assembled monolayer on the other material, wherein the material comprises at least one material selected from the group consisting of: octadecyltrichlorosilane, phenethyltrichlorosilane, hexamethyldisilazane, allyltrimethoxysilane, or perfluorooctyltrichlorosilanem, and patterning the self-assembled monolayer to reveal a portion of the first material. A method of forming a charge pattern in a microchip includes depositing a first material as one of either a solution processed material or a vapor deposited material to generate a first polarity or first magnitude of charge, depositing a second material as a vapor deposited material to generate a second polarity or second magnitude of charge, and immersing the microchip in a non-polar fluid comprising one selected from the group consisting of: an isoparafinnic liquid, a hydrocarbon liquid and dodecane.

A module includes a substrate, a component mounted on a top surface that is one principal surface of the substrate, a first shielding film provided on a top surface and a side surface of the component, a sealing resin provided on the top surface of the substrate and seals the component, and a second shielding film provided on a top surface of the sealing resin. A hole is provided on a top surface of the sealing resin, to reach at least a part of the first shielding film. The second shielding film disposed in the hole is brought into contact with the first shielding film at positions facing a top surface and a side surface of the component.

A method for forming a semiconductor device includes forming a laser marking buried within a semiconductor substrate and thinning the semiconductor substrate from a backside of the semiconductor substrate. For example, a semiconductor device includes a semiconductor substrate located in a semiconductor package. A laser marking is buried within the semiconductor substrate. For example, another semiconductor device includes a semiconductor substrate. A laser marking is located at a backside surface of the semiconductor substrate. Further, a portion of the backside surface located adjacent to the laser marking is free of recast material.

A semiconductor device includes a package, a control terminal group including at least three control terminals inputting a control signal to a semiconductor element and projecting from a side surface of a first side out of the first side and a second side opposite to the first side of the package, and a main terminal group including at least three main terminals energizing the semiconductor element with a main current and projecting from a side surface of the second side. Middle portions of the two respective terminals of the control terminal group and the main terminal group are provided with stoppers for preventing over-insertion into the substrate. A middle portion of at least one terminal of at least any one of the terminal groups of the control terminal group and the main terminal group is provided with stoppers for identifying a rated current of the semiconductor device.

A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.

The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.

Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling a back surface electrode of the semiconductor chip with an upper surface of the chip mounting part; a plurality of inner lead parts and a plurality of outer lead parts electrically coupled with an electrode pad of the semiconductor chip through wires; and a sealing body for sealing the semiconductor chip and the wires. Further, a recess is formed in a peripheral region of the back surface of the semiconductor chip. The recess has a first surface extending to join the back surface and a second surface extending to join the first surface. Also, a metal film is formed over the first surface and the second surface of the recess.

A semiconductor device includes a monocrystalline substrate of a material which does not have a liquid phase at atmospheric pressure, and an identification mark disposed on or in the substrate comprising an amorphous region of the material or a region of the material deviated from stoichiometry.

A semiconductor device according to the present embodiment includes a wiring substrate having a wiring layer. A first semiconductor chip is provided above the wiring substrate. A metallic wire connects the first semiconductor chip and the wiring substrate to each other. A silicon chip is provided above the first semiconductor chip and covers above the metallic wire. A resin layer seals the first semiconductor chip and the silicon chip, and the metallic wire. The silicon chip is insulated from the wiring substrate.

According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe. The leadframe may include: a plurality of pins extending from the center support structure; a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and a bar connecting the plurality of pins remote from the center support structure. The method may further include: bonding the IC chip to at least some of the plurality of pins; encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound; removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins; plating the exposed portion of the plurality of pins; and cutting the IC package free from the bar by sawing through the encapsulated lead frame along the groove using a first saw width less than a width of the groove.