Disclosed herein is a wafer processing method for removing an annular reinforcing portion from a wafer having a device area, the annular reinforcing portion being formed around the device area. The wafer processing method includes the steps of supporting the wafer through an adhesive tape to an annular frame, forming a mark corresponding to a notch at a position radially inside a boundary portion between the annular reinforcing portion and the device area, cutting the boundary portion together with the adhesive tape to thereby separate the annular reinforcing portion from the device area, and moving the annular reinforcing portion supported through the adhesive tape to the annular frame away from a holding table to thereby remove the annular reinforcing portion from the wafer.

Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

A film resist is a member for being bonded to a main surface of a substrate, which main surface is provided with a mark. The film resist includes a cutout for the mark to be checked.

A method includes receiving a device having a first layer and a second layer over the first layer, the first layer having a first overlay mark. The method further includes forming a first resist pattern over the second layer, the first resist pattern having a second overlay mark. The method further includes performing a first overlay measurement using the second overlay mark in the first resist pattern and the first overlay mark; and performing one or more first manufacturing processes, thereby transferring the second overlay mark into the second layer and removing the first resist pattern. The method further includes performing one or more second manufacturing processes that include forming a third layer over the second layer. After the performing of the one or more second manufacturing processes, the method includes performing a second overlay measurement using the second overlay mark in the second layer and the first overlay mark.

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment.

A polishing composition eliminating protrusions around a laser mark in wafer polishing processes, the manufacturing method therefor and a polishing method using the composition. The polishing composition including silica particles and water, wherein: the composition includes a tetraalkylammonium ion such that the mass ratio of the ion to SiO.sub.2 of the silica particles is 0.400 to 1.500:1, and the mass ratio of SiO.sub.2 dissolved in the polishing composition to SiO.sub.2 is 0.100 to 1.500:1; the tetraalkylammonium ion is derived from a compound selected from the group made of an alkali silicate, a hydroxide, a carbonate, a sulfate, and a halide while the ion is contained in the polishing composition in 0.2% by mass to 8.0% by mass; and the dissolved SiO.sub.2 is derived from a tetraalkylammonium silicate, a potassium silicate, a sodium silicate, or a mixture of any of these.

A method of determining a lateral misregistration between levels of a semiconductor structure comprises imaging at least one first alignment mark in a first level of the structure and at least one second alignment mark in a second level of the structure. A digital image of the first and second alignment marks is formed, each of which are defined by a set of points having an x-value and a y-value. The x-values and y-values of points defining the first alignment mark and points defining the second alignment mark are averaged to determine a center of the first alignment mark and a center of the second alignment mark. An x-coordinate and a y-coordinate of the center of the first alignment mark is subtracted from the respective x-coordinate and y-coordinate of the center of the second alignment mark to determine a lateral misregistration between the first level and the second level. Related methods of forming a semiconductor wafer, semiconductor assembles and metrology tools for use in implementing the methods are disclosed.

Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.