A transition device for a flexible device and a production method therefor, and a method for fabricating a flexible device are provided. The transition device includes a functional component and a transition base. The functional component has a first surface for mounting with a base and a second surface opposite to the first surface, and the transition base is bonded to the second surface of the functional component by an adhesive layer.

The present disclosure provides a method that includes receiving a circuit layout that includes circuit features and a mark pattern to be formed on a same material layer over an integrated circuit (IC) substrate, the circuit features being longitudinally oriented along a first direction and being distanced from each other along a second direction that is orthogonal to the first direction; fragmenting the mark pattern to generate a fragmented mark pattern having fragmented mark features such that the fragmented mark features are configured in parallel and are longitudinally oriented along a third direction; and generating a modified circuit layout for circuit fabrication, the modified circuit layout including the circuit features and the fragmented mark pattern.

A semiconductor chip includes a mounting surface having a plurality of first conductive contacts and a second conductive contact, wherein each of the first contacts in the plurality is arranged in a regularly spaced apart array such that centroids of immediately adjacent ones of the first contacts are separated from one another in a first direction by a first distance, each of the first contacts in the plurality have an identical first lateral extent, and the second conductive contact is arranged between two of the first conductive contacts in the first direction such that first and second distances between the at least one second conductive contact and the two of the first conductive contacts are each less than the first distance.

A circuit die may include an outermost circuit layer having electrical transmission routing and an alignment target overlying the outermost circuit layer.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

a mounting device and a mounting method is provided with which, after lowering a mounting head holding a chip component in a direction perpendicular to a substrate to bring the chip component into close contact with the substrate subsequent to positioning the chip component and the substrate, a control unit causes a recognition mechanism to start a parallel recognition operation of a chip recognition mark and a substrate recognition mark and recognize the chip recognition mark and the substrate recognition mark through the mounting head in a mounted state in which the chip component is in close contact with the substrate, and calculates mounting position accuracy of the chip component and the substrate.

A mounting device comprises a recognition mechanism and a control unit. The recognition mechanism recognizes a chip recognition mark and a substrate recognition mark through a mounting head and from above the mounting head and is movable in an in-plane direction of a substrate surface of a substrate. The control unit is connected to the recognition mechanism, calculates an amount of misalignment between a chip component and the substrate from position information about the chip recognition mark and the substrate recognition mark obtained from the recognition mechanism, and performs positioning by driving the mounting head and/or the substrate stage according to the amount of misalignment. The recognition mechanism has a chip recognition sensor for recognizing the chip recognition mark and a substrate recognition sensor for recognizing the substrate recognition mark provided independently so that focal positions thereof are different via a common optical axis path.

A device used for semiconductor metrology includes a substrate and a plurality of pieces from one or more semiconductor wafers. Each piece of the plurality of pieces is bonded to the substrate at a respective position on the substrate. Each piece of the plurality of pieces includes a respective instance of a measurement test structure and an alignment mark. Each piece of the plurality of pieces has a known location from the one or more semiconductor wafers.

The present publication discloses a circuit-board structure, including a conductor layer on an insulating material layer, and a conductor pattern on top of the conductor foil. A component is attached to the conductor foil and the conductor pattern, the component embedded at least in part in adhesive which attaches the component to the insulating material layer. A recess is formed in the conductor foil and the insulating material layer, and contact openings are in the insulating material layer at locations of contact areas of the component. Conductor material of the conductor foil is not present outside the conductor pattern, and the conductor foil is located between the conductor pattern and the insulating material layer.

A microelectronic device includes a die less than 300 microns thick, and an interface tile. Die attach leads on the interface tile are electrically coupled to die terminals on the die through interface bonds. The microelectronic device includes an interposer between the die and the interface tile. Lateral perimeters of the die, the interposer, and the interface tile are aligned with each other. The microelectronic device may be formed by forming the interface bonds and an interposer layer, while the die is part of a wafer and the interface tile is part of an interface lamina. Kerfs are formed through the interface lamina, through the interposer, and partway through the wafer, around a lateral perimeter of the die. Material is subsequently removed at a back surface of the die to the kerfs, so that a thickness of the die is less than 300 microns.