A die bond head apparatus has a die bond head body coupled to a die bond head motion table, a die holder motion table mounted on the die bond head body and a die holder which is operative in use to secure a semiconductor die to a substrate. The die holder is positionable by the die holder motion table independently of the die bond head motion table.

A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

A resin shaping device configured to cure a resin placed in a mold in a state in which the mold is pressed against a substrate, the resin shaping device comprising: a substrate holding unit configured to hold the substrate in an orientation such that a forming face for forming a resin part on the substrate faces vertically downward; a head configured to hold the mold from vertically below; a head drive unit configured to cause the head to face a position for formation of a resin part on the substrate, and then cause vertically upward movement of the head so that the head approaches the substrate holding unit and presses the mold from vertically below the substrate; and a resin curing unit configured to cure the resin placed in the mold in a state in which the mold is pressed against the substrate.

A semiconductor package system includes a substrate, a first and a second semiconductor package, a first thermal conductive layer, a first passive device, and a heat radiation structure. The first and second semiconductor package and first passive device may be mounted on a top surface of the substrate. The first semiconductor package may include a first semiconductor chip that includes a plurality of logic circuits. The first thermal conductive layer may be on the first semiconductor package. The heat radiation structure may be on the first thermal conductive layer, the second semiconductor package, and the first passive device. The heat radiation structure may include a first bottom surface physically contacting the first thermal conductive layer, and a second bottom surface at a higher level than that of the first bottom surface. The second bottom surface may be on the second semiconductor package and/or the first passive device.

A system includes a separation tool that separates a carrier wafer to form a plurality of chiplet carriers. The carrier wafer having sheets of thin film material attached. A sensor and processor of the system determine an orientation of the portions of the sheets of thin film material relative to the chiplets to determine a mapping therebetween. A fluid carrier of the system places the chiplet carriers on an assembly surface in a disordered pattern. The system includes a micro assembler that arranges the chiplet carriers from the disordered pattern to a predetermined pattern based on the mapping. A carrier of the system transfers the portions of the thin film material from the chiplet carriers to a target substrate.

A system includes a separation tool that separates a carrier wafer to form a plurality of chiplet carriers. The carrier wafer having sheets of thin film material attached. A sensor and processor of the system determine an orientation of the portions of the sheets of thin film material relative to the chiplets to determine a mapping therebetween. A fluid carrier of the system places the chiplet carriers on an assembly surface in a disordered pattern. The system includes a micro assembler that arranges the chiplet carriers from the disordered pattern to a predetermined pattern based on the mapping. A carrier of the system transfers the portions of the thin film material from the chiplet carriers to a target substrate.

A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 μm; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

An optoelectronic component that emits electromagnetic radiation from a radiation exit surface of the optoelectronic component includes a radiation-emitting semiconductor chip that produces electromagnetic radiation, and a marker element applied to the radiation exit surface of the optoelectronic component, the marker element including a dye substance that can be removed from the radiation exit surface using a solvent and/or is permeable to the electromagnetic radiation of the optoelectronic component, wherein the dye substance includes a resin into which fluorescent particles are introduced that convert electromagnetic radiation of a first wavelength range into electromagnetic radiation of a second wavelength range, the first wavelength range and the second wavelength range being within the ultraviolet spectral range.

Sheets of a thin film material are attached to a carrier wafer. The carrier wafer and the attached sheets of thin film material are separated to form chiplet carriers. Each chiplet carrier includes a portion of the sheets of thin film material attached to a portion of the carrier wafer. The chiplet carriers are placed on an assembly surface in a random pattern. The chiplet carriers are arranged from the random pattern to a predetermined pattern, and the portions of the thin film material are transferred from the chiplet carriers to a target substrate.

In certain embodiments, a method for designing a semiconductor device includes generating a two-dimensional design for fabricating chiplets on a semiconductor substrate. The chiplets are component levels for a multi-chip integrated circuit. The two-dimensional design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The second chiplet is adjacent to the first chiplet on the semiconductor substrate. The second layout is a mirror image of the first layout across a reference line shared by the first chiplet and the second chiplet. The first surface of the first chiplet and the first surface of the second chiplet are both either top surfaces or bottom surfaces. The method further includes generating a photomask according to the design.