A lead frame includes a die paddle, a first lead, a second lead, an extending portion and at least one supporting portion. The first lead includes a first main portion and a first I/O portion opposite to the first main portion. The second lead includes a second main portion and a second I/O portion opposite to the second main portion. The first lead and the second lead surround the die paddle. The extending portion extends from the first main portion of the first lead. The supporting portion is connected to the extending portion.

An alignment mark at a position that overlaps an area in which an anisotropic conductive film is pasted, and to accurately perform alignment using an image captured by a camera. An alignment method in which an electronic component is mounted on the obverse surface of a transparent substrate with a conductive adhesive agent interposed therebetween, a substrate-side alignment mark and a component-side alignment mark are adjusted from the captured image, and the position at which the electronic component is mounted on the transparent substrate is aligned, wherein in the conductive adhesive agent, conductive particles are in a regular arrangement as viewed from a planar perspective, and in the captured image, the outside edges of the alignment marks exposed between the conductive particles are intermittently visible as line segments (S) along the imaginary line segments of the outside edges of the alignment mark.

A semiconductor chip includes: a semiconductor substrate having driver circuitry configured to drive an array of electronic devices; a metal layer above the semiconductor substrate, the metal layer having an array of contacts electrically connected to the driver circuitry and configured to provide an electrical connection between the semiconductor chip and the array of electronic devices; and a plurality of structures formed in the metal layer and/or in a layer between the metal layer and the semiconductor substrate, the plurality of structures being visually unobstructed at a side of the metal layer which faces away from the semiconductor substrate. Each structure of the plurality of structures is physically encoded with a pattern that corresponds to a location of an individual pair of contacts within the array of contacts or a location of a group of adjacent pairs of contacts within the array of contacts.

A die bond head apparatus has a die bond head body coupled to a die bond head motion table, a die holder motion table mounted on the die bond head body and a die holder which is operative in use to secure a semiconductor die to a substrate. The die holder is positionable by the die holder motion table independently of the die bond head motion table.

A bond head assembly for a bonding machine is provided. The bond head assembly includes a body portion and a bonding tool for bonding a semiconductor element to a substrate. The bonding tool is secured to the body portion. The bond head assembly also includes at least one reflective optical element carried by the bond head assembly. The at least one reflective optical element is configured to be positioned along an optical path of the bonding machine such that a vision system of the bonding machine is configured to view a portion of the semiconductor element while being carried by the bonding tool prior to bonding of the semiconductor element to the substrate.

Sheets of a thin film material are attached to a carrier wafer. The carrier wafer and the attached sheets of thin film material are separated to form chiplet carriers. Each chiplet carrier includes a portion of the sheets of thin film material attached to a portion of the carrier wafer. The chiplet carriers are placed on an assembly surface in a random pattern. The chiplet carriers are arranged from the random pattern to a predetermined pattern, and the portions of the thin film material are transferred from the chiplet carriers to a target substrate.

A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.

A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Various embodiments may relate to a method of forming a photonic integrated circuit package (PIC). The method may include forming a redistribution layer (RDL) over a carrier. The method may also include forming a through hole or cavity on the redistribution layer. The method may additionally include providing a stop-ring structure, the stop-ring structure including a ring of suitable material, the stop-ring structure defining a hollow space, over the redistribution layer so that the hollow space is over the through hole or cavity. The method may further include arranging a photonic integrated circuit (PIC) die over the redistribution layer so that the photonic integrated circuit (PIC) die is on the stop-ring structure. The method may also include forming a molded package by forming a mold structure to at least partially cover the photonic integrated circuit (PIC) die to form the photonic integrated circuit package.

A semiconductor package system includes a substrate, a first and a second semiconductor package, a first thermal conductive layer, a first passive device, and a heat radiation structure. The first and second semiconductor package and first passive device may be mounted on a top surface of the substrate. The first semiconductor package may include a first semiconductor chip that includes a plurality of logic circuits. The first thermal conductive layer may be on the first semiconductor package. The heat radiation structure may be on the first thermal conductive layer, the second semiconductor package, and the first passive device. The heat radiation structure may include a first bottom surface physically contacting the first thermal conductive layer, and a second bottom surface at a higher level than that of the first bottom surface. The second bottom surface may be on the second semiconductor package and/or the first passive device.