A semiconductor wafer includes a wafer body including an active layer having a first crystal orientation and having first and second surfaces opposing each other, and a support layer having a second crystal orientation different from the first crystal orientation and having third and fourth surfaces opposing each other, a bevel portion that extends along an outer periphery of the wafer body to connect the first surface to the fourth surface, and a notch portion formed at a predetermined depth in a direction from the outer periphery of the wafer body toward a center portion of the wafer body. The bevel portion includes a first beveled surface connected to the first surface and a second beveled surface connected to the fourth surface. The first beveled surface has a width in a radial direction of the wafer body that is 300 μm or less.

A radio frequency (RF) integrated circuit may include a die having passive components including at least one pair of capacitors covered by a first dielectric layer supported by the die. The RF integrated circuit may also include an inline pad structure coupled to the at least one pair of capacitors proximate an edge of the die. The inline pad structure may include a first portion and a second portion extending into a dicing street toward the edge of the die and covered by at least a second dielectric layer.

Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.

A marking structure where marking visibility is improved is provided. In a semiconductor device having a marking structure, the marking structure includes: a body for marking having a surface; a first mark group having a first concave portion formed in the surface; a second mark group having a second concave portion formed adjacent to the first concave portion in the surface. The first concave portion and the second concave portion differ in shape so that they may cause light reflection differently. Thus, visibility of the marking structure can be improved.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.

Provided is a semiconductor device manufacturing method including a process of annealing a semiconductor wafer in a state in which a supported portion on a lower surface of the semiconductor wafer is supported by using a supporting portion, wherein the supported portion includes one or a plurality of supporting portions and the supporting portion includes one or a plurality of supporting portions, the method comprising: forming impurity regions including a first impurity in a region which is overlapped with the supported portion in a top view and which is apart from an edge of the semiconductor wafer; annealing the semiconductor wafer in a state in which the lower surface of the semiconductor wafer is supported by the supporting portion; and removing the impurity regions by removing a region including the lower surface of the semiconductor wafer.

Disclosed herein is a wafer processing method for removing an annular reinforcing portion from a wafer having a device area, the annular reinforcing portion being formed around the device area. The wafer processing method includes the steps of supporting the wafer through an adhesive tape to an annular frame, forming a mark corresponding to a notch at a position radially inside a boundary portion between the annular reinforcing portion and the device area, cutting the boundary portion together with the adhesive tape to thereby separate the annular reinforcing portion from the device area, and moving the annular reinforcing portion supported through the adhesive tape to the annular frame away from a holding table to thereby remove the annular reinforcing portion from the wafer.

A substrate stacking apparatus that stacks first and second substrates on each other, by forming a contact region where the first substrate held by a first holding section and the second substrate held by a second holding section contact each other, at one portion of the first and second substrates, and expanding the contact region from the one portion by releasing holding of the first substrate by the first holding section, wherein an amount of deformation occurring in a plurality of directions at least in the first substrate differs when the contact region expands, and the substrate stacking apparatus includes a restricting section that restricts misalignment between the first and second substrates caused by a difference in the amount of deformation. In the substrate stacking apparatus above, the restricting section may restrict the misalignment such that an amount of the misalignment is less than or equal to a prescribed value.

An apparatus for separating a wafer from a carrier includes a platform having an upper surface, a tape feeding unit, a first robot arm, and a controller coupled to the platform. The controller is configured to mount a wafer frame, by using the tape feeding unit, on a wafer of a wafer assembly on the upper surface of the platform. The wafer assembly includes the wafer, a carrier, and a layer of wax between the wafer and the carrier. The controller is also configured to heat the upper surface of the platform to a predetermined temperature and separate, by the first robot arm, the wafer and the wafer frame mounted thereon from the carrier.

Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.