Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.

IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

A substrate stacking apparatus that stacks first and second substrates on each other, by forming a contact region where the first substrate held by a first holding section and the second substrate held by a second holding section contact each other, at one portion of the first and second substrates, and expanding the contact region from the one portion by releasing holding of the first substrate by the first holding section, wherein an amount of deformation occurring in a plurality of directions at least in the first substrate differs when the contact region expands, and the substrate stacking apparatus includes a restricting section that restricts misalignment between the first and second substrates caused by a difference in the amount of deformation. In the substrate stacking apparatus above, the restricting section may restrict the misalignment such that an amount of the misalignment is less than or equal to a prescribed value.

A semiconductor wafer includes a wafer body including an active layer having a first crystal orientation and having first and second surfaces opposing each other, and a support layer having a second crystal orientation different from the first crystal orientation and having third and fourth surfaces opposing each other, a bevel portion that extends along an outer periphery of the wafer body to connect the first surface to the fourth surface, and a notch portion formed at a predetermined depth in a direction from the outer periphery of the wafer body toward a center portion of the wafer body. The bevel portion includes a first beveled surface connected to the first surface and a second beveled surface connected to the fourth surface. The first beveled surface has a width in a radial direction of the wafer body that is 300 μm or less.

A semiconductor device and a method of fabricating the same are disclosed. A reference direction for a substrate is parallel to a first or second crystallographic direction, and a patterned hard mask layer is distributed along the first crystallographic direction. For substrates with notches oriented in different crystallographic directions, the patterned mask layer may be used as a mask for forming trenches in the substrate surface. When viewed normal to a cross-section perpendicular to the substrate, each trench has a cross-sectional width decreasing from the substrate surface toward the inside of the substrate. This allows the semiconductor device to have increased light absorption and conversion efficiency. Forming the trenches by wet etching can avoid increased dark current due to damage to the trenches’ side surfaces that may be caused by the use of a dry etching process. Thus, an effective improvement in terms of dark current can be achieved.

A microLED mass transfer stamping system includes a stamp substrate with an array of trap sites, each configured with a columnar-shaped recess to temporarily secure a keel extended from a bottom surface of a microLED. In the case of surface mount microLEDs, the keel is electrically nonconductive. In the case of vertical microLEDs, the keel is an electrically conductive second electrode. The stamping system also includes a fluidic assembly carrier substrate with an array of wells having a pitch separating adjacent wells that matches the pitch separating the stamp substrate trap sites. A display substrate includes an array of microLED pads with the same pitch as the trap sites. The stamp substrate top surface is pressed against the display substrate, with each trap site interfacing a corresponding microLED site, and the microLEDs are transferred. Fluidic assembly stamp substrates are also presented for use with microLEDs having keels or axial leads.

The present invention provides a wafer notch leveling device, which comprises a body, a first rotating portion, a positioning portion, a power portion, and a control unit. The body has a support portion and a pivot portion is provided at each terminal of the body, the pivot portion pivotally connects a plurality of supporting arms. The first rotating portion and the positioning portion are electrically connected with the power portion. The power portion is electrically connected with the control unit. Especially, when a plurality of wafers are placed on the support portion and fixed, the first rotating portion is electrically connected with the power portion through the control unit to drive the plurality of wafers to rotate the wafers, a notch on the wafer is leveled through the positioning portion.

An alignment mark includes an alignment region, a peripheral region and a shielding region. The alignment region has an outer contour; the peripheral region is disposed around at least a part of the outer contour of the alignment region; the shielding region is disposed around at least a part of the outer contour of the alignment region and is non-overlapped with the peripheral region; and the alignment region and the shielding region are opaque, and the peripheral region is at least partially transparent.

An apparatus for transferring a wafer includes a main body, a first support installed in the main body, a sensor support fixed to the first support, a finger member slidably installed along the first support to transfer the wafer and positioned at a lower level than the sensor support, three sensors each including a light emitter installed on the first support and a light receiver installed on the sensor support, the three sensors respectively configured to detect three points of an edge of the wafer seated on the finger member, and a controller connected to the three sensors, wherein the controller is configured to determine whether any of the three points of the edge of the wafer is detected from a notch of the wafer based on signals received from the sensors.

The present invention provides a wafer notch leveling device, which comprises a body, a first rotating portion, a positioning portion, a power portion, and a control unit. The body has a support portion and a pivot portion is provided at each terminal of the body, the pivot portion pivotally connects a plurality of supporting arms. The first rotating portion and the positioning portion are electrically connected with the power portion. The power portion is electrically connected with the control unit. Especially, when a plurality of wafers are placed on the support portion and fixed, the first rotating portion is electrically connected with the power portion through the control unit to drive the plurality of wafers to rotate the wafers, a notch on the wafer is leveled through the positioning portion.