An integrated circuit device includes: a substrate having an active surface, an inactive surface, a first region and a second region; a device structure on the active surface, and including individual devices disposed in the first region and a target through-region disposed in the second region; a multilayer wiring structure including wiring layers, wherein at least one wiring layer among the wiring layers has a landing pad overlapping the target through-region; and a through-via structure connected to the landing pad by penetrating through the second region and the target through-region, wherein the target through-region includes first insulating material patterns and dummy device patterns, wherein the first insulating material patterns each have a first area, wherein the dummy device patterns are on the active surface and each have a second area smaller than the first area, and wherein the first insulating material patterns are alternatively arranged with the dummy device patterns.

A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

A semiconductor device includes first and second conductive parts, a first bonding wire connecting the first and second conductive parts and having a non-flat portion between opposite ends thereof so that a portion between the opposite ends is away from the first and second conductive parts, a case having a housing space to accommodate the first and second conductive parts, including a sidewall having first to fourth lateral faces surrounding the housing space to form a rectangular shape in a plan view, and a cover disposed on the sidewall, a sealing member filling the case to seal the first bonding wire, and a first stress relaxer for relieving a stress in the first bonding wire. The first bonding wire extends from the second lateral face toward the fourth lateral face, and the first stress relaxer is positioned between the first bonding wire and the first lateral face.

A semiconductor device includes first and second conductive parts, a first bonding wire connecting the first and second conductive parts and having a non-flat portion between opposite ends thereof so that a portion between the opposite ends is away from the first and second conductive parts, a case having a housing space to accommodate the first and second conductive parts, including a sidewall having first to fourth lateral faces surrounding the housing space to form a rectangular shape in a plan view, and a cover disposed on the sidewall, a sealing member filling the case to seal the first bonding wire, and a first stress relaxer for relieving a stress in the first bonding wire. The first bonding wire extends from the second lateral face toward the fourth lateral face, and the first stress relaxer is positioned between the first bonding wire and the first lateral face.

A bonded assembly includes a first semiconductor die that includes first semiconductor devices, and a first pad-level dielectric layer and embedding first bonding pads; and a second semiconductor die that includes second semiconductor devices, and a second pad-level dielectric layer embedding second bonding pads that includes a respective second pad base portion. Each of the first bonding pads includes a respective first pad base portion and a respective first metal alloy material portion having a higher coefficient of thermal expansion (CTE) than the respective first pad base portion. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

A bonded assembly includes a first semiconductor die that includes first semiconductor devices, and a first pad-level dielectric layer and embedding first bonding pads; and a second semiconductor die that includes second semiconductor devices, and a second pad-level dielectric layer embedding second bonding pads that includes a respective second pad base portion. Each of the first bonding pads includes a respective first pad base portion and a respective first metal alloy material portion having a higher coefficient of thermal expansion (CTE) than the respective first pad base portion. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.

A semiconductor device includes a semiconductor element layer including a semiconductor substrate including a bump area and a dummy bump area. A TSV structure is in the bump area and vertically extends through the semiconductor substrate, a first topmost line is in the bump area and on the TSV structure and electrically connected to the TSV structure, a signal bump is in the bump area and has a first width in a first direction and is electrically connected to the TSV structure via the first topmost line, a second topmost line is in the dummy bump area and has the same vertical level as a vertical level of the first topmost line and extends in the first direction, and a dummy bump is in the dummy bump area and contacts the second topmost line and has a second width in the first direction larger than the first width.