A method of producing a semiconductor module arrangement includes providing a first subassembly having a number N1 of first adjustment openings, a second subassembly having a number N2 of second adjustment openings and a third subassembly having a plurality of adjustment pins which are fixedly connected to one another, the first subassembly, the second subassembly and the third subassembly being independent of one another and not connected to one another. The first subassembly, the second subassembly and the third subassembly are arranged relative to one another in such a way that each of the adjustment pins engages into one of the first adjustment openings and/or into one of the second adjustment openings.

A method of producing a semiconductor module arrangement includes providing a first subassembly having a number N1 of first adjustment openings, a second subassembly having a number N2 of second adjustment openings and a third subassembly having a plurality of adjustment pins which are fixedly connected to one another, the first subassembly, the second subassembly and the third subassembly being independent of one another and not connected to one another. The first subassembly, the second subassembly and the third subassembly are arranged relative to one another in such a way that each of the adjustment pins engages into one of the first adjustment openings and/or into one of the second adjustment openings.

A light-emitting device, includes a substrate with a top surface; a first light-emitting structure unit and a second light-emitting structure unit separately formed on the top surface and adjacent to each other, and wherein the first light-emitting structure unit includes a first sidewall and a second sidewall; a trench between the first and the second light-emitting structure units; and an electrical connection arranged on the first sidewall and the second light-emitting structure unit, and electrically connecting the first light-emitting structure unit and the second light-emitting structure unit; wherein the first sidewall connects to the top surface; wherein the first sidewall faces the second light-emitting structure units, and the second sidewall is not between the first light-emitting structure unit and the second light-emitting structure unit; and wherein the second sidewall is steeper than the first sidewall.

A light-emitting device, includes a substrate with a top surface; a first light-emitting structure unit and a second light-emitting structure unit separately formed on the top surface and adjacent to each other, and wherein the first light-emitting structure unit includes a first sidewall and a second sidewall; a trench between the first and the second light-emitting structure units; and an electrical connection arranged on the first sidewall and the second light-emitting structure unit, and electrically connecting the first light-emitting structure unit and the second light-emitting structure unit; wherein the first sidewall connects to the top surface; wherein the first sidewall faces the second light-emitting structure units, and the second sidewall is not between the first light-emitting structure unit and the second light-emitting structure unit; and wherein the second sidewall is steeper than the first sidewall.

A camera array, an imaging device and/or a method for capturing image that employ a plurality of imagers fabricated on a substrate is provided. Each imager includes a plurality of pixels. The plurality of imagers include a first imager having a first imaging characteristics and a second imager having a second imaging characteristics. The images generated by the plurality of imagers are processed to obtain an enhanced image compared to images captured by the imagers. Each imager may be associated with an optical element fabricated using a wafer level optics (WLO) technology.

A camera array, an imaging device and/or a method for capturing image that employ a plurality of imagers fabricated on a substrate is provided. Each imager includes a plurality of pixels. The plurality of imagers include a first imager having a first imaging characteristics and a second imager having a second imaging characteristics. The images generated by the plurality of imagers are processed to obtain an enhanced image compared to images captured by the imagers. Each imager may be associated with an optical element fabricated using a wafer level optics (WLO) technology.

A method of joining a metal-ceramic substrate having metalization on at least one side to a metal body by using a metal alloy is disclosed. The metal body has a thickness of less than 1.0 mm, and the metal alloy contains aluminum and has a liquidus temperature of greater than 450° C. The resulting metal-ceramic module provides a strong bond between the metal body and the ceramic substrate. The resulting module is useful as a circuit carrier in electronic appliances, with the metal body preferably functioning as a cooling body.

A method of joining a metal-ceramic substrate having metalization on at least one side to a metal body by using a metal alloy is disclosed. The metal body has a thickness of less than 1.0 mm, and the metal alloy contains aluminum and has a liquidus temperature of greater than 450° C. The resulting metal-ceramic module provides a strong bond between the metal body and the ceramic substrate. The resulting module is useful as a circuit carrier in electronic appliances, with the metal body preferably functioning as a cooling body.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.