Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

Anisotropic conductive films, each including an insulating adhesive layer and conductive particles insulating adhesive layer in a lattice-like manner. Among center distances between an arbitrary conductive particle and conductive particles adjacent to the conductive particle, the shortest distance to the conductive particle is a first center distance; the next shortest distance is a second center distance. These center distances are 1.5 to 5 times the conductive particles' diameter. The arbitrary conductive particle, conductive particle spaced apart from the conductive particle by the first center distance, conductive particle spaced apart from the conductive particle by first center distance or second center distance form an acute triangle. Regarding this acute triangle, an acute angle formed between a straight line orthogonal to a first array direction passing through the conductive particles and second array direction passing through conductive particles being 18 to 35°. These anisotropic conductive films have stable connection reliability in COG connection.

Anisotropic conductive films, each including an insulating adhesive layer and conductive particles insulating adhesive layer in a lattice-like manner. Among center distances between an arbitrary conductive particle and conductive particles adjacent to the conductive particle, the shortest distance to the conductive particle is a first center distance; the next shortest distance is a second center distance. These center distances are 1.5 to 5 times the conductive particles' diameter. The arbitrary conductive particle, conductive particle spaced apart from the conductive particle by the first center distance, conductive particle spaced apart from the conductive particle by first center distance or second center distance form an acute triangle. Regarding this acute triangle, an acute angle formed between a straight line orthogonal to a first array direction passing through the conductive particles and second array direction passing through conductive particles being 18 to 35°. These anisotropic conductive films have stable connection reliability in COG connection.

A method for evaluating pickup property of a dicing/die-bonding integrated film including a base layer, an adhesive, and a bonding adhesive layer in order, the method including preparing a laminate including the dicing/die-bonding integrated film and a wafer having a thickness of 10 to 100 μm laminated on the bonding adhesive layer, singulating the wafer into a plurality of chips having an area of 9 mm.sup.2 or less, pushing a center portion of the chip from a side of the base layer, and measuring a peeling strength when an edge of the chip is peeled off from the adhesive layer.

A method for evaluating pickup property of a dicing/die-bonding integrated film including a base layer, an adhesive, and a bonding adhesive layer in order, the method including preparing a laminate including the dicing/die-bonding integrated film and a wafer having a thickness of 10 to 100 μm laminated on the bonding adhesive layer, singulating the wafer into a plurality of chips having an area of 9 mm.sup.2 or less, pushing a center portion of the chip from a side of the base layer, and measuring a peeling strength when an edge of the chip is peeled off from the adhesive layer.

A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube. The second insulating encapsulant laterally encapsulates the dummy die and the memory cube.

A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube. The second insulating encapsulant laterally encapsulates the dummy die and the memory cube.

A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.

A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.