A connection structure including: a first circuit member having a plurality of first electrodes; a second circuit member having a plurality of second electrodes; and an intermediate layer having a plurality of bonding portions electrically connecting the first electrodes and the second electrodes, in which at least one of the first electrode and the second electrode that are connected by the bonding portion is a gold electrode, and 90% or more of the plurality of bonding portions include a first region containing a tin-gold alloy and connecting the first electrode and the second electrode and a second region containing bismuth and being in contact with the first region.

In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first substrate including a center region and an edge region distal from the center region, a first circuit layer positioned on the first substrate, a center power pad positioned in the first circuit layer and above the center region, an edge power pad positioned in the first circuit layer, above the edge region, and electrically coupled to the center power pad, a redistribution power pattern positioned above the first circuit layer and electrically coupled to the center power pad, and an edge power via positioned between the edge power pad and the redistribution power pattern, and electrically connecting the edge power pad and the redistribution power pattern. The first substrate, the center power pad, the edge power pad, the redistribution power pattern, and the edge power via together configure a first semiconductor die.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first substrate including a center region and an edge region distal from the center region, a first circuit layer positioned on the first substrate, a center power pad positioned in the first circuit layer and above the center region, an edge power pad positioned in the first circuit layer, above the edge region, and electrically coupled to the center power pad, a redistribution power pattern positioned above the first circuit layer and electrically coupled to the center power pad, and an edge power via positioned between the edge power pad and the redistribution power pattern, and electrically connecting the edge power pad and the redistribution power pattern. The first substrate, the center power pad, the edge power pad, the redistribution power pattern, and the edge power via together configure a first semiconductor die.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.

A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.