A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.

A semiconductor device includes a semiconductor substrate, a TiW layer arranged on the semiconductor substrate a Ti layer arranged on the TiW layer, a Ni alloy layer arranged on the Ti layer, and an Ag layer arranged on the Ni alloy layer, wherein the Ag layer and the Ni alloy layer comprise side faces fabricated by at least one wet etching process, and wherein the Ti layer and the TiW layer comprise side faces fabricated by a dry etching process.

A semiconductor device includes a semiconductor substrate, a TiW layer arranged on the semiconductor substrate a Ti layer arranged on the TiW layer, a Ni alloy layer arranged on the Ti layer, and an Ag layer arranged on the Ni alloy layer, wherein the Ag layer and the Ni alloy layer comprise side faces fabricated by at least one wet etching process, and wherein the Ti layer and the TiW layer comprise side faces fabricated by a dry etching process.

A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate according to the following steps: forming a reservoir in a surface layer on the first contact surface, at least partially filling the reservoir with a first educt or a first group of educts, contacting the first contact surface with the second contact surface for formation of a prebond connection, and forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with a second educt contained in a reaction layer of the second substrate.

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

A package structure includes a semiconductor substrate, an under bump metallurgy layer, and at least one bump. The under bump metallurgy layer is disposed on the semiconductor substrate. The bump is disposed on the under bump metallurgy layer, and the bump includes a first portion and a second portion under the first portion, wherein a top surface of the first portion of the bump includes a flat portion and a rounded portion.

A package structure includes a semiconductor substrate, an under bump metallurgy layer, and at least one bump. The under bump metallurgy layer is disposed on the semiconductor substrate. The bump is disposed on the under bump metallurgy layer, and the bump includes a first portion and a second portion under the first portion, wherein a top surface of the first portion of the bump includes a flat portion and a rounded portion.

A method for making and a semiconductor device comprises a silicon die including a metal contact region and, at least one passivation layer covering the semiconductor die and patterned such as to form an opening to the metal contact region of the semiconductor die. A continuous part of a contact layer comprises a refractory metal, and overlaps and completely covers the opening in the at least one passivation layer to contact the metal contact region in the opening and adhere to the at least one passivation layer along the entire edge of the continuous part. The contact layer comprises at least an adhesion layer and at least a diffusion barrier layer. A noble metal layer is arranged over the contact layer and completely covers the continuous part to adhere to the at least one passivation layer around the edge of the continuous part.

A method for making and a semiconductor device comprises a silicon die including a metal contact region and, at least one passivation layer covering the semiconductor die and patterned such as to form an opening to the metal contact region of the semiconductor die. A continuous part of a contact layer comprises a refractory metal, and overlaps and completely covers the opening in the at least one passivation layer to contact the metal contact region in the opening and adhere to the at least one passivation layer along the entire edge of the continuous part. The contact layer comprises at least an adhesion layer and at least a diffusion barrier layer. A noble metal layer is arranged over the contact layer and completely covers the continuous part to adhere to the at least one passivation layer around the edge of the continuous part.

There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices. The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 m. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175 C. or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.