A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

A silicon carbide semiconductor device, including a semiconductor substrate containing silicon carbide, a bonding wire, and a surface electrode of an aluminum alloy containing silicon, the surface electrode being provided on a surface of the semiconductor substrate, and having a joint portion to which the bonding wire is bonded. The surface electrode has a plurality of silicon nodules formed therein, which include a number of the silicon nodules formed in the joint portion. One of the number of the silicon nodules is of a dendrite structure, and is included at an area percentage of at least 10% relative to a total area of the number of the silicon nodules in the joint portion.

A silicon carbide semiconductor device, including a semiconductor substrate containing silicon carbide, a bonding wire, and a surface electrode of an aluminum alloy containing silicon, the surface electrode being provided on a surface of the semiconductor substrate, and having a joint portion to which the bonding wire is bonded. The surface electrode has a plurality of silicon nodules formed therein, which include a number of the silicon nodules formed in the joint portion. One of the number of the silicon nodules is of a dendrite structure, and is included at an area percentage of at least 10% relative to a total area of the number of the silicon nodules in the joint portion.

The present invention has as its object the provision of a bonding wire for semiconductor devices mainly comprised of Ag, in which bonding wire for semiconductor devices, the bond reliability demanded for high density mounting is secured and simultaneously a sufficient, stable bond strength is realized at a ball bond, no neck damage occurs even in a low loop, the leaning characteristic is excellent, and the FAB shape is excellent. To solve this problem, the bonding wire for semiconductor devices according to the present invention contains one or more of Be, B, P, Ca, Y, La, and Ce in a total of 0.031 at % to obtain a 0.180 at %, further contains one or more of In, Ga, and Cd in a total of 0.05 at % to 5.00 at %, and has a balance of Ag and unavoidable impurities. Due to this, it is possible to obtain a bonding wire for semiconductor devices sufficiently forming an intermetallic compound layer at a ball bond interface to secure the bond strength of the ball bond, not causing neck damage even in a low loop, having a good leaning characteristic, and having a good FAB shape.