Patent classifications
H01L2924/01008
Semiconductor structure and fabrication method thereof
A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer.
Semiconductor structure and fabrication method thereof
A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer.
Hollow metal pillar packaging scheme
An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.
Method for bonding substrates
This invention relates to a method for bonding of a first contact area of a first at least largely transparent substrate to a second contact area of a second at least largely transparent substrate, on at least one of the contact areas an oxide being used for bonding, from which an at least largely transparent interconnection layer is formed with an electrical conductivity of at least 10e1 S/cm.sup.2 (measurement: four point method, relative to temperature of 300K) and an optical transmittance greater than 0.8 (for a wavelength range from 400 nm to 1500 nm) on the first and second contact area.
Method for bonding substrates
This invention relates to a method for bonding of a first contact area of a first at least largely transparent substrate to a second contact area of a second at least largely transparent substrate, on at least one of the contact areas an oxide being used for bonding, from which an at least largely transparent interconnection layer is formed with an electrical conductivity of at least 10e1 S/cm.sup.2 (measurement: four point method, relative to temperature of 300K) and an optical transmittance greater than 0.8 (for a wavelength range from 400 nm to 1500 nm) on the first and second contact area.
NOBLE METAL-COATED COPPER WIRE FOR BALL BONDING
A noble metal-coated copper wire for ball bonding, with a wire diameter between 10 m or more, and 25 m or less, includes a core material having a copper alloy having a copper purity of 98 mass % or higher, and a noble metal-coating layer formed on the core material. The noble metal-coating layer includes a palladium cavitating layer containing palladium; at least one element selected from the group consisting of Group 13 to 16 elements or an oxygen element, finely dispersed in the palladium; and a diffusion layer formed of copper diffused into the palladium. The noble metal-coating layer may include a palladium cavitating layer containing palladium, at least one element selected from the group consisting of Group 13 to 16 elements or an oxygen element, finely dispersed therein, and a nickel intermediate layer disposed between the core material and the noble metal-coating layer.
NOBLE METAL-COATED COPPER WIRE FOR BALL BONDING
A noble metal-coated copper wire for ball bonding, with a wire diameter between 10 m or more, and 25 m or less, includes a core material having a copper alloy having a copper purity of 98 mass % or higher, and a noble metal-coating layer formed on the core material. The noble metal-coating layer includes a palladium cavitating layer containing palladium; at least one element selected from the group consisting of Group 13 to 16 elements or an oxygen element, finely dispersed in the palladium; and a diffusion layer formed of copper diffused into the palladium. The noble metal-coating layer may include a palladium cavitating layer containing palladium, at least one element selected from the group consisting of Group 13 to 16 elements or an oxygen element, finely dispersed therein, and a nickel intermediate layer disposed between the core material and the noble metal-coating layer.
Wafer bonding using boron and nitrogen based bonding stack
A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities.