H01L2924/01016

Bonding wire for semiconductor device

Provided is a Pd coated Cu bonding wire for a semiconductor device capable of sufficiently obtaining bonding reliability of a ball bonded portion in a high temperature environment of 175° C. or more, even when the content of sulfur in the mold resin used in the semiconductor device package increases. The bonding wire for a semiconductor device comprises a Cu alloy core material; and a Pd coating layer formed on a surface of the Cu alloy core material; and contains 0.03 to 2% by mass in total of one or more elements selected from Ni, Rh, Ir and Pd in the bonding wire and further 0.002 to 3% by mass in total of one or more elements selected from Li, Sb, Fe, Cr, Co, Zn, Ca, Mg, Pt, Sc and Y. The bonding wire can be sufficiently obtained bonding reliability of a ball bonded portion in a high temperature environment of 175° C. or more, even when the content of sulfur in the mold resin used in the semiconductor device package increases by being used.

Bonding wire for semiconductor device

Provided is a Pd coated Cu bonding wire for a semiconductor device capable of sufficiently obtaining bonding reliability of a ball bonded portion in a high temperature environment of 175° C. or more, even when the content of sulfur in the mold resin used in the semiconductor device package increases. The bonding wire for a semiconductor device comprises a Cu alloy core material; and a Pd coating layer formed on a surface of the Cu alloy core material; and contains 0.03 to 2% by mass in total of one or more elements selected from Ni, Rh, Ir and Pd in the bonding wire and further 0.002 to 3% by mass in total of one or more elements selected from Li, Sb, Fe, Cr, Co, Zn, Ca, Mg, Pt, Sc and Y. The bonding wire can be sufficiently obtained bonding reliability of a ball bonded portion in a high temperature environment of 175° C. or more, even when the content of sulfur in the mold resin used in the semiconductor device package increases by being used.

Semiconductor memory device structure

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

SEMICONDUCTOR MEMORY DEVICE STRUCTURE
20220157753 · 2022-05-19 ·

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH.sub.2 species. This may be accomplished by exposing the bonding layer to an NH.sub.4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

PALLADIUM-COATED COPPER BONDING WIRE, WIRE BONDING STRUCTURE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

The bonding wire being a Pd-coated copper bonding wire includes: a copper core material; and a Pd layer and containing a sulfur group element, in which with respect to the total of copper, Pd, and the sulfur group element, a concentration of Pd is 1.0 mass % to 4.0 mass % and a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of S is 5 mass ppm to 2 mass ppm, a concentration of Se is 5 mass ppm to 20 mass ppm, or a concentration of Te is 15 mass ppm to 50 mass ppm or less. A wire bonding structure includes a Pd-concentrated region with the concentration of Pd being 2.0 mass % or more relative to the total of Al, copper, and Pd near a bonding surface of an Al-containing electrode of a semiconductor chip and a ball bonding portion.

PALLADIUM-COATED COPPER BONDING WIRE, WIRE BONDING STRUCTURE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

The bonding wire being a Pd-coated copper bonding wire includes: a copper core material; and a Pd layer and containing a sulfur group element, in which with respect to the total of copper, Pd, and the sulfur group element, a concentration of Pd is 1.0 mass % to 4.0 mass % and a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of S is 5 mass ppm to 2 mass ppm, a concentration of Se is 5 mass ppm to 20 mass ppm, or a concentration of Te is 15 mass ppm to 50 mass ppm or less. A wire bonding structure includes a Pd-concentrated region with the concentration of Pd being 2.0 mass % or more relative to the total of Al, copper, and Pd near a bonding surface of an Al-containing electrode of a semiconductor chip and a ball bonding portion.

PALLADIUM-COATED COPPER BONDING WIRE, MANUFACTURING METHOD OF PALLADIUM-COATED COPPER BONDING WIRE, WIRE BONDING STRUCTURE USING THE SAME, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A Pd-coated Cu bonding wire of an embodiment contains Pd of 1.0 to 4.0 mass %, and a S group element of 50 mass ppm or less in total (S of 5.0 to 12.0 mass ppm, Se of 5.0 to 20.0 mass ppm, or Te of 15.0 to 50 mass ppm). At a crystal plane of a cross section of the wire, a <100> orientation ratio is 15% or more, and a <111> orientation ratio is 50% or less. When a free air ball is formed on the wire and a tip portion is analyzed, a Pd-concentrated region is observed on the surface thereof.

METHOD AND STRUCTURES FOR LOW TEMPERATURE DEVICE BONDING
20220130787 · 2022-04-28 ·

Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.

METHOD AND STRUCTURES FOR LOW TEMPERATURE DEVICE BONDING
20220130787 · 2022-04-28 ·

Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.