Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.

A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include at least two side-gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.