A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.

An imaging device to which a simple mounting method can be applied is configured. The imaging device is provided with an imaging element, a wiring substrate, and a sealing portion. The imaging element is provided with an image pickup chip over which an light transmitting portion transmitting incident light is arranged and which generates an image signal on the basis of the incident light that has passed through the light transmitting portion, and a pad which is arranged on a bottom surface of the image pickup chip different from a surface on which the light transmitting portion is arranged, which the pad transmitting the generated image signal. The wiring substrate has wiring connected to the pad and extending to a region outside the imaging element, and has the imaging element arranged on a surface thereof. The sealing portion is arranged adjacent to a side surface which is a surface adjacent to the bottom surface of the imaging element, and seals the imaging element.

An integrated electronic device including: a main body delimited by a front surface; a top conductive region extending within the main body, starting from the front surface; a first dielectric region extending on the front surface; and a barrier structure, arranged on the first dielectric region. A first aperture extends through the barrier structure and the first dielectric region; the first aperture is delimited at bottom by the top conductive region. The integrated electronic device further includes a contact structure including at least a first conductive region extending within the first aperture, in direct contact with the top conductive region and the barrier structure.

An integrated electronic device including: a main body delimited by a front surface; a top conductive region extending within the main body, starting from the front surface; a first dielectric region extending on the front surface; and a barrier structure, arranged on the first dielectric region. A first aperture extends through the barrier structure and the first dielectric region; the first aperture is delimited at bottom by the top conductive region. The integrated electronic device further includes a contact structure including at least a first conductive region extending within the first aperture, in direct contact with the top conductive region and the barrier structure.

An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.

An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.

A bonded assembly includes a first semiconductor die that includes first semiconductor devices, and a first pad-level dielectric layer and embedding first bonding pads; and a second semiconductor die that includes second semiconductor devices, and a second pad-level dielectric layer embedding second bonding pads that includes a respective second pad base portion. Each of the first bonding pads includes a respective first pad base portion and a respective first metal alloy material portion having a higher coefficient of thermal expansion (CTE) than the respective first pad base portion. Each of the second bonding pads is bonded to a respective one of the first bonding pads.