A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.

Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a mold resin covering the surface of the substrate so as to embed therein the electronic component; a magnetic film formed of a composite magnetic material obtained by dispersing magnetic fillers in a thermosetting resin material, the magnetic film covering upper and side surfaces of the molding resin and an edge portion of the front surface exposed to aside surface of the substrate; and a metal film connected to the power supply pattern and covering the molding resin through the magnetic film.

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a mold resin covering the surface of the substrate so as to embed therein the electronic component; a laminated structure of a magnetic film and a metal film, the laminated structure covering at least an upper surface of the molding resin. The metal film is connected to the power supply pattern, and a resistance value at an interface between the magnetic film and the metal film is equal to or larger than 10.sup.6Ω.

A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition including a base resin; a filler; a colorant; and a thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature.

An object of the present invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on the element formation layer, and a conductive film serving as an antenna, which is provided on the insulating film. The insulating film has a groove. The conductive film is provided along the surface of the insulating film and the groove. The groove of the insulating film may be provided to pass through the insulating film. Alternatively, a concave portion may be provided in the insulating film so as not to pass through the insulating film. A structure of the groove is not particularly limited, and for example, the groove can be provided to have a tapered shape, etc.

An integrated fan-out package including a die, an insulating encapsulation, a filler, and a redistribution circuit structure is provided. The insulating encapsulation encapsulates sidewalls of the die, and the insulating encapsulation includes a recess on a top surface thereof. The filler covers the top surface of the insulating encapsulation and is being at least partially filled in the recess. The redistribution circuit structure covers an active surface of the die and the filler while being electrically connected to the die. The redistribution structure includes a dielectric layer covering the die and the filler. In addition, a method of manufacturing integrated fan-out packages is also provided.

Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.