A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

An electronic device includes a first part, and a circuit plate including a circuit substrate, a plating film made of a plating material and being disposed on a front surface of the substrate. The plating film includes a first part region on which the first part is disposed via a first solder, and a liquid-repellent region extending along a periphery side of the first part region in a surface layer of the plating film, and having a liquid repellency greater than a liquid repellency of the plating film. The liquid-repellent region includes a resist region. The plating film includes a remaining portion between the liquid-repellent region and the front surface of the circuit substrate in a thickness direction of the plating film orthogonal to the front surface. The remaining portion is made of the plating material and is free of the oxidized plating material.

An electronic device includes a first part, and a circuit plate including a circuit substrate, a plating film made of a plating material and being disposed on a front surface of the substrate. The plating film includes a first part region on which the first part is disposed via a first solder, and a liquid-repellent region extending along a periphery side of the first part region in a surface layer of the plating film, and having a liquid repellency greater than a liquid repellency of the plating film. The liquid-repellent region includes a resist region. The plating film includes a remaining portion between the liquid-repellent region and the front surface of the circuit substrate in a thickness direction of the plating film orthogonal to the front surface. The remaining portion is made of the plating material and is free of the oxidized plating material.

A semiconductor device including an insulating circuit board. The insulating circuit board has an insulating plate, a plurality of circuit patterns disposed on a front surface of the insulating plate, any adjacent two of the circuit patterns having a gap therebetween, each circuit pattern having at least one corner, each corner being in a corner area that covers the corner and a portion of each gap adjacent to the corner, and a buffer material containing resin, applied at a plurality of corner areas, to fill the gaps in the plurality of corner areas.

A semiconductor device including an insulating circuit board. The insulating circuit board has an insulating plate, a plurality of circuit patterns disposed on a front surface of the insulating plate, any adjacent two of the circuit patterns having a gap therebetween, each circuit pattern having at least one corner, each corner being in a corner area that covers the corner and a portion of each gap adjacent to the corner, and a buffer material containing resin, applied at a plurality of corner areas, to fill the gaps in the plurality of corner areas.

Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

A forming method of a semiconductor package includes the following steps. A first die is provided. The first die includes a first bonding structure and a first seal ring, the first bonding structure is formed at a first side of the first die, a first portion of the first seal ring is formed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring. A second die is provided. The second die includes a second bonding structure. The first die and the second die are bonded onto an integrated circuit through the first bonding structure and the second bonding structure.

A forming method of a semiconductor package includes the following steps. A first die is provided. The first die includes a first bonding structure and a first seal ring, the first bonding structure is formed at a first side of the first die, a first portion of the first seal ring is formed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring. A second die is provided. The second die includes a second bonding structure. The first die and the second die are bonded onto an integrated circuit through the first bonding structure and the second bonding structure.

One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.