A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

A method of joining a semiconductor die to a substrate includes: applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 μm and a lower melting point than both metal regions; forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the die; and setting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the melting point of the preform and the soldering temperature.

There is provided an Ag alloy bonding wire for semiconductor devices which exhibits a favorable bond reliability in a high-temperature environment even when using a mold resin of high S content and can suppress a chip damage at the time of ball bonding. The Ag alloy bonding wire is characterized by containing at least one element selected from the group consisting of Pd and Pt (hereinafter referred to as a “first element”) and at least one element selected from the group consisting of P, Cr, Zr and Mo (hereinafter referred to as a “second element”) so as to satisfy

[00001]$0.05\le \text{x}1\le 3.0,\text{and}$

[00002]$15\le \text{x}2\le 700$

where x1 is a total concentration of the first element [at.%] and x2 is a total concentration of the second element [at. ppm], with the balance including Ag.

There is provided an Ag alloy bonding wire for semiconductor devices which exhibits a favorable bond reliability in a high-temperature environment even when using a mold resin of high S content and can suppress a chip damage at the time of ball bonding. The Ag alloy bonding wire is characterized by containing at least one element selected from the group consisting of Pd and Pt (hereinafter referred to as a “first element”) and at least one element selected from the group consisting of P, Cr, Zr and Mo (hereinafter referred to as a “second element”) so as to satisfy

[00001]$0.05\le \text{x}1\le 3.0,\text{and}$

[00002]$15\le \text{x}2\le 700$

where x1 is a total concentration of the first element [at.%] and x2 is a total concentration of the second element [at. ppm], with the balance including Ag.

A solder material for use in electronic assembly, the solder material comprising: solder layers; and a core layer comprising a core material, the core layer being sandwiched between the solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder.

A solder material for use in electronic assembly, the solder material comprising: solder layers; and a core layer comprising a core material, the core layer being sandwiched between the solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder.

A quantum computing system can include a first substrate including one or more quantum control devices. The quantum computing system can include a second substrate including one or more quantum circuit elements. The quantum computing system can include one or more tin contact bonds formed on the first substrate and the second substrate. The tin contact bonds can bond the first substrate to the second substrate. The tin contact bonds can be or can include tin, such as a tin alloy.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.