Patent classifications
H01L2924/01039
Semiconductor integrated circuit device
In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.
Semiconductor integrated circuit device
In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.
LEAD-FREE COLUMN INTERCONNECT
Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.
LEAD-FREE COLUMN INTERCONNECT
Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.
Stack package and methods of manufacturing the same
A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer.
Stack package and methods of manufacturing the same
A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer.
Electronic device, electronic module and methods for fabricating the same
An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
Electronic device, electronic module and methods for fabricating the same
An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
Electronic device having a plated antenna and/or trace, and methods of making and using the same
An electronic device, and methods of manufacturing the same are disclosed. The method of manufacturing the electronic device includes forming a first metal layer on a first substrate, forming an integrated circuit or a discrete electrical component on a second substrate, forming electrical connectors on input and/or output terminals of the integrated circuit or discrete electrical component, forming a second metal layer on the first metal layer, the second metal layer improving adhesion and/or electrical connectivity of the first metal layer to the electrical connectors on the integrated circuit or discrete electrical component, and electrically connecting the electrical connectors to the second metal layer.
Electronic device having a plated antenna and/or trace, and methods of making and using the same
An electronic device, and methods of manufacturing the same are disclosed. The method of manufacturing the electronic device includes forming a first metal layer on a first substrate, forming an integrated circuit or a discrete electrical component on a second substrate, forming electrical connectors on input and/or output terminals of the integrated circuit or discrete electrical component, forming a second metal layer on the first metal layer, the second metal layer improving adhesion and/or electrical connectivity of the first metal layer to the electrical connectors on the integrated circuit or discrete electrical component, and electrically connecting the electrical connectors to the second metal layer.