Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

There is provided a novel Al wiring material that suppresses an increase in cold strength and exhibits a favorable high-temperature reliability. The Al wiring material contains one or more selected from the group consisting of Er, Yb and Gd so as to satisfy 0.001≤x1≤0.6 where x1 is a total content thereof [% by mass], with the balance comprising Al.

The present disclosure is directed to a hybrid conductive ink including: silver nanoparticles and eutectic low melting point alloy particles, wherein a weight ratio of the eutectic low melting point alloy particles and the silver nanoparticles ranges from 1:20 to 1:5. Also provided herein are methods of forming an interconnect including a) depositing a hybrid conductive ink on a conductive element positioned on a substrate, wherein the hybrid conductive ink comprises silver nanoparticles and eutectic low melting point alloy particles, the eutectic low melting point alloy particles and the silver nanoparticles being in a weight ratio from about 1:20 to about 1:5; b) placing an electronic component onto the hybrid conductive ink; c) heating the substrate, conductive element, hybrid conductive ink and electronic component to a temperature sufficient i) to anneal the silver nanoparticles in the hybrid conductive ink and ii) to melt the low melting point eutectic alloy particles, wherein the melted low melting point eutectic alloy flows to occupy spaces between the annealed silver nanoparticles, d) allowing the melted low melting point eutectic alloy of the hybrid conductive ink to harden and fuse to the electronic component and the conductive element, thereby forming an interconnect. Electrical circuits including conductive traces and, optionally, interconnects formed with the hybrid conductive ink are also provided.

The present disclosure is directed to a hybrid conductive ink including: silver nanoparticles and eutectic low melting point alloy particles, wherein a weight ratio of the eutectic low melting point alloy particles and the silver nanoparticles ranges from 1:20 to 1:5. Also provided herein are methods of forming an interconnect including a) depositing a hybrid conductive ink on a conductive element positioned on a substrate, wherein the hybrid conductive ink comprises silver nanoparticles and eutectic low melting point alloy particles, the eutectic low melting point alloy particles and the silver nanoparticles being in a weight ratio from about 1:20 to about 1:5; b) placing an electronic component onto the hybrid conductive ink; c) heating the substrate, conductive element, hybrid conductive ink and electronic component to a temperature sufficient i) to anneal the silver nanoparticles in the hybrid conductive ink and ii) to melt the low melting point eutectic alloy particles, wherein the melted low melting point eutectic alloy flows to occupy spaces between the annealed silver nanoparticles, d) allowing the melted low melting point eutectic alloy of the hybrid conductive ink to harden and fuse to the electronic component and the conductive element, thereby forming an interconnect. Electrical circuits including conductive traces and, optionally, interconnects formed with the hybrid conductive ink are also provided.

An inter-substrate bond structure includes an adhesion layer that attached to a first substrate, and an outer gas-permeable layer coupled to the adhesion layer. The outer gas-permeable layer expands and fractures in response to absorbing a gas. The inter-substrate bond structure includes an outer bond layer coupled to the outer gas-permeable layer. The outer bond layer forms an initial thermocompression bond with a mating layer on a second substrate. The initial thermocompression bond bonds the first substrate to the second substrate with the inter-substrate bond structure. The fracture in the inter-substrate bond structure debonds the first substrate from the second substrate while leaving a first portion of the inter-substrate bond structure attached to the first substrate.

A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.

A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.

Provided is a package including: a die having an upper surface and including at least one conductive pad disposed adjacent to the upper surface; a first pillar structure over the die; and a second pillar structure aside the first pillar structure, wherein the second pillar structure is electrically connected to the conductive pad of the die, and defining a recess portion recessed from a side surface of the second pillar structure, wherein the second pillar structure and the conductive pad have different conductivities.

Provided is a package including: a die having an upper surface and including at least one conductive pad disposed adjacent to the upper surface; a first pillar structure over the die; and a second pillar structure aside the first pillar structure, wherein the second pillar structure is electrically connected to the conductive pad of the die, and defining a recess portion recessed from a side surface of the second pillar structure, wherein the second pillar structure and the conductive pad have different conductivities.

A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.