H01L2924/01045

Semiconductor device and method of forming the same

A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.

Semiconductor device and method of forming the same

A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.

Protective surface layer on under bump metallurgy for solder joining

A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS
20220059484 · 2022-02-24 ·

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

ELECTRONIC COMPONENT
20170309591 · 2017-10-26 ·

An electric component comprising a terminal electrode and a hot-melt polymer layer formed on the terminal electrode, wherein the hot-melt polymer layer comprises (i) 100 parts by weight of a metal powder and (ii) 1 to 30 parts by weight of a polymer, wherein melt mass-flow rate (MFR) of the polymer is 0.5 to 20 g/10 min. at 120 to 200° C. and 0.3 to 8 kgf.

Semiconductor package with conductive clip

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Semiconductor device

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

Conductive composition and conductive molded article

The present invention relates to a conductive composition containing a conductive metal powder and a resin component, in which the conductive metal powder contains at least a metal flake having a crystalline structure in which a metal crystal grows in a flake shape, and the resin component contains an aromatic amine skeleton.

Conductive composition and conductive molded article

The present invention relates to a conductive composition containing a conductive metal powder and a resin component, in which the conductive metal powder contains at least a metal flake having a crystalline structure in which a metal crystal grows in a flake shape, and the resin component contains an aromatic amine skeleton.

PROCESS FOR ELECTRICALLY CONNECTING CONTACT SURFACES OF ELECTRONIC COMPONENTS

A process for electrically connecting contact surfaces of electronic components by capillary wedge bonding a round wire of 8 to 80 μm to the contact surface of a first electronic component, forming a wire loop, and stitch bonding the wire to the contact surface of a second electronic component, wherein the wire comprises a wire core having a silver or silver-based wire core with a double-layered coating comprised of a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold.