An antenna module includes an antenna substrate, a first semiconductor package, disposed on the antenna substrate, including a first connection member including one or more first redistribution layers, electrically connected to the antenna substrate, and a first semiconductor chip disposed on the first connection member, and a second semiconductor package, disposed on the antenna substrate to be spaced apart from the first semiconductor package, including a second connection member including one or more second redistribution layers, electrically connected to the antenna substrate, and a second semiconductor chip disposed on the second connection member. The first semiconductor chip and the second semiconductor chip are different types of semiconductor chips.

A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump.

A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump.

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

In a layered bonding material 10, a coefficient of linear expansion of a base material 11 is 5.5 to 15.5 ppm/K and a first surface and a second surface of the base material 11 are coated with pieces of lead-free solder 12a and 12b.

In a layered bonding material 10, a coefficient of linear expansion of a base material 11 is 5.5 to 15.5 ppm/K and a first surface and a second surface of the base material 11 are coated with pieces of lead-free solder 12a and 12b.

A method of manufacturing a semiconductor device, the method including: preparing an insulated circuit substrate including a conductive plate; partially fixing a plate-like bonding member onto the conductive plate so as to make a positioning of the bonding member in a horizontal direction; mounting a semiconductor chip on the bonding member; and heating and melting the bonding member so as to form a bonding layer for bonding the insulated circuit substrate and the semiconductor chip each other.

A method of manufacturing a semiconductor device, the method including: preparing an insulated circuit substrate including a conductive plate; partially fixing a plate-like bonding member onto the conductive plate so as to make a positioning of the bonding member in a horizontal direction; mounting a semiconductor chip on the bonding member; and heating and melting the bonding member so as to form a bonding layer for bonding the insulated circuit substrate and the semiconductor chip each other.

A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.