A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus. The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the light emitting device 10, and the second resin molding 50 which contains YAG fluorescent material and covers the light emitting device 10. The first resin molding 40 has the recess 40c comprising the bottom surface 40a and the side surface 40b formed therein, and the second resin molding 50 is placed in the recess 40c. The first resin molding 40 is formed from a thermosetting resin such as epoxy resin by the transfer molding process, and the second resin molding 50 is formed from a thermosetting resin such as silicone resin.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing a second lithography step on the third level; perform processing steps to form first memory cells within the second level and second memory cells within the third level, where first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and deposit a gate electrode for the second and the third transistors simultaneously.

A 3D semiconductor device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where a second metal layer is disposed atop the first metal layer; a plurality of logic gates including the first metal layer and first transistors; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the mini arrays includes at least two rows by two columns of memory cells, where each memory cell includes one of the second transistors or one of the third transistors, and where one of the second transistors is self-aligned to one of the third transistors, being processed following a same lithography step.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and first single crystal transistors; a first metal layer; a second metal layer disposed atop the first metal layer; second transistors disposed atop of the second metal layer; third transistors disposed atop of the second transistors, where at least one of the third transistors includes at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate, and where a distance from at least one of the third transistors to at least one of the first transistors is less than 2 microns.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said first transistors controls power delivery for at least one of said second transistor, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, a first metal layer (includes interconnection of first transistors), and a second metal layer, where first transistors' interconnection includes forming logic gates; a plurality of second transistors disposed atop, at least in part, of logic gates; a plurality of third transistors disposed atop, at least in part, of the second transistors; a third metal layer disposed above, at least in part, the third transistors; a global grid to distribute power and overlaying, at least in part, the third metal layer; a local grid to distribute power to the logic gates, the local grid is disposed below, at least in part, the second transistors, where the second transistors are aligned to the first transistors with less than 40 nm misalignment, where at least one of the second transistors includes a metal gate.