Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

A semiconductor device includes a semiconductor chip, a bump contract, and encapsulating layer, an insulating layer, and a connection terminal.

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

A semiconductor package including a semiconductor chip having a chip pad thereon; a first insulating layer; a redistribution line pattern on the first insulating layer; a redistribution via pattern through the first insulating layer to connect the chip pad to the redistribution line pattern; a second insulating layer covering the redistribution line pattern and including a first part having a first thickness and a second part having a second thickness. the second part being inward relative to the first part; a first conductive pillar through the first part and connected to the redistribution line pattern; a second conductive pillar through the second part and connected to the redistribution line pattern; a first connection pad on the first conductive pillar; a second connection pad on the second conductive pillar; a first connection terminal contacting the first connection pad; and a second connection terminal contacting the second connection pad.

A semiconductor package including a semiconductor chip having a chip pad thereon; a first insulating layer; a redistribution line pattern on the first insulating layer; a redistribution via pattern through the first insulating layer to connect the chip pad to the redistribution line pattern; a second insulating layer covering the redistribution line pattern and including a first part having a first thickness and a second part having a second thickness. the second part being inward relative to the first part; a first conductive pillar through the first part and connected to the redistribution line pattern; a second conductive pillar through the second part and connected to the redistribution line pattern; a first connection pad on the first conductive pillar; a second connection pad on the second conductive pillar; a first connection terminal contacting the first connection pad; and a second connection terminal contacting the second connection pad.

A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.