H01L2924/01081

BARRIER STRUCTURES FOR UNDERFILL CONTAINMENT

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

Lead-free solder alloy, solder joint, solder paste composition, electronic circuit board, and electronic device

According to one aspect of the present invention, a lead-free solder alloy includes 2% by mass or more and 3.1% by mass or less of Ag, more than 0% by mass and 1% by mass or less of Cu, 1% by mass or more and 5% by mass or less of Sb, 3.1% by mass or more and 4.5% by mass or less of Bi, 0.01% by mass or more and 0.25% by mass or less of Ni, and Sn.

Lead-free solder alloy, solder joint, solder paste composition, electronic circuit board, and electronic device

According to one aspect of the present invention, a lead-free solder alloy includes 2% by mass or more and 3.1% by mass or less of Ag, more than 0% by mass and 1% by mass or less of Cu, 1% by mass or more and 5% by mass or less of Sb, 3.1% by mass or more and 4.5% by mass or less of Bi, 0.01% by mass or more and 0.25% by mass or less of Ni, and Sn.

BONDED ASSEMBLY CONTAINING OXIDATION BARRIERS, HYBRID BONDING, OR AIR GAP, AND METHODS OF FORMING THE SAME

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

BONDED ASSEMBLY CONTAINING OXIDATION BARRIERS, HYBRID BONDING, OR AIR GAP, AND METHODS OF FORMING THE SAME

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

SEMICONDUCTOR LASER COMPONENT AND METHOD OF PRODUCING A SEMICONDUCTOR LASER COMPONENT
20200176948 · 2020-06-04 ·

A semiconductor laser component including a semiconductor chip arranged to emit laser radiation, a cladding that is electrically insulating and covers the semiconductor chip in places, and a bonding layer that electrically conductively connects the semiconductor chip to a first connection point, wherein the semiconductor chip includes a cover surface, a bottom surface, a first front surface, a second front surface, a first side surface and a second side surface, the first front surface is arranged to decouple the laser beam, the cladding covers the semiconductor chip at least in places on the cover surface, the second front surface, the first side surface and the second side surface, and the bonding layer on the cladding extends from the cover surface to the first connection point.

SEMICONDUCTOR LASER COMPONENT AND METHOD OF PRODUCING A SEMICONDUCTOR LASER COMPONENT
20200176948 · 2020-06-04 ·

A semiconductor laser component including a semiconductor chip arranged to emit laser radiation, a cladding that is electrically insulating and covers the semiconductor chip in places, and a bonding layer that electrically conductively connects the semiconductor chip to a first connection point, wherein the semiconductor chip includes a cover surface, a bottom surface, a first front surface, a second front surface, a first side surface and a second side surface, the first front surface is arranged to decouple the laser beam, the cladding covers the semiconductor chip at least in places on the cover surface, the second front surface, the first side surface and the second side surface, and the bonding layer on the cladding extends from the cover surface to the first connection point.

SINTERED MATERIAL, CONNECTION STRUCTURE, COMPOSITE PARTICLE, JOINING COMPOSITION, AND METHOD FOR MANUFACTURING SINTERED MATERIAL

Provided are a sintered material excellent in both thermal stress and bonding strength; a connection structure comprising the sintered material; a composition for bonding with which the sintered material can be produced; and a method for producing the sintered material. The sintered material comprises a base portion, one or more buffer portions, and one or more filling portions. The buffer portions and the filling portions are dispersed in the base portion. The base portion is a metal sintered body, each buffer portion is formed from at least one of a pore and a material that is not the same as that of the sintered body, and each filling portion is formed from at least one of particles and fibers. The sintered material satisfies A>B, where A is the kurtosis of volume distribution of the base portions in a three-dimensional image of the sintered material, and B is the kurtosis of volume distribution of the base portions in a three-dimensional image of the sintered material from which the filling portions are removed.