Standardized photon building blocks are used to make both discrete light emitters as well as array products. Each photon building block has one or more LED chips mounted on a substrate. No electrical conductors pass between the top and bottom surfaces of the substrate. The photon building blocks are supported by an interconnect structure that is attached to a heat sink. Landing pads on the top surface of the substrate of each photon building block are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors on the interconnect structure are electrically coupled to the LED dice in the photon building blocks through the contact pads and landing pads. The bottom surface of the interconnect structure is coplanar with the bottom surfaces of the substrates of the photon building blocks.

Methods and structures are provided for wafer-level packaging of light-emitting diodes (LEDs). An array of LED die are mounted on a packaging substrate. The substrate may include an array of patterned metal contacts on a front side. The metal contacts may be in electrical communication with control logic formed in the substrate. The LEDs mounted on the packaging substrate may also be encapsulated individually or in groups and then singulated, or the LEDs mounted on the packaging substrate may be integrated with a micro-mirror array or an array of lenses.

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.

Standardized photon building blocks are used to make both discrete light emitters as well as array products. Each photon building block has one or more LED chips mounted on a substrate. No electrical conductors pass between the top and bottom surfaces of the substrate. The photon building blocks are supported by an interconnect structure that is attached to a heat sink. Landing pads on the top surface of the substrate of each photon building block are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors on the interconnect structure are electrically coupled to the LED dice in the photon building blocks through the contact pads and landing pads. The bottom surface of the interconnect structure is coplanar with the bottom surfaces of the substrates of the photon building blocks.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

LED packages and related methods are provided. The LED packages can include a submount having a top and bottom surface and a plurality of top electrically conductive elements on the top surface of the submount. An LED can be disposed on one of the top electrically conductive elements. The LED can emit a dominant wavelength generally between approximately 600 nm and approximately 650 nm, and more particularly between approximately 610 nm and approximately 630 nm when an electrical signal is applied to the top electrically conductive elements. A bottom thermally conductive element can be provided on the bottom surface and is not in electrical contact with the top electrically conductive elements. A lens can be disposed over the LED. The LED packages can have improved lumen performances, lower thermal resistances, improved efficiencies, and longer operational lifetimes.

A semiconductor device 10 includes a pair of electrodes 16 and a conductive connection member 21 electrically bonded to the pair of electrodes 16. At least a portion of a perimeter of a bonding surface 24 of at least one of the pair of electrodes 16 and the conductive connection member 21 includes an electromigration reducing area 22.

A semiconductor device 10 includes a pair of electrodes 16 and a conductive connection member 21 electrically bonded to the pair of electrodes 16. At least a portion of a perimeter of a bonding surface 24 of at least one of the pair of electrodes 16 and the conductive connection member 21 includes an electromigration reducing area 22.

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.