A semiconductor device, the device comprising: a first substrate; a first metal layer disposed over said substrate; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said plurality of transistors comprise single crystal silicon; a third metal layer disposed over said first level; a fourth metal layer disposed over said third metal layer, wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error; and a via disposed through said first level, wherein said via has a diameter of less than 450 nm, wherein said fourth metal layer provides a global power distribution, and wherein said via is directly connected to at least one of said plurality of transistors.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the first level thickness is less than two microns.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the fourth metal layer provides a global power distribution, and where a typical thickness of the fourth metal layer is at least 50% greater than a typical thickness of the third metal.

A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, a connection path from the fifth metal layer to the second metal layer, where the connection path includes a via disposed through the second level, where the via has a diameter of less than 450 nm, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the first level thickness is less than two microns.

A semiconductor device including: a silicon layer including a single crystal silicon and a plurality of first transistors; a first metal layer disposed over the silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer, a second level including a plurality of second transistors, the first level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the second level, the second level thickness is less than two microns, the fifth metal layer includes a global power distribution grid, where a fifth metal layer typical thickness is greater than a second metal layer typical thickness by at least 50%.

A semiconductor device including: a silicon layer including a single crystal silicon and a plurality of first transistors; a first metal layer disposed over the silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer, a second level including a plurality of second transistors, the first level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the second level, the second level thickness is less than two microns, the fifth metal layer includes a global power distribution grid, where a fifth metal layer typical thickness is greater than a second metal layer typical thickness by at least 50%.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer over the first silicon layer; a second metal layer over the first metal layer; a first level including a plurality of transistors over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer over the first level; a fourth metal layer over the third metal layer, where the fourth metal layer is aligned to the first metal layer with less than 40 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer over the first silicon layer; a second metal layer over the first metal layer; a first level including a plurality of transistors over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer over the first level; a fourth metal layer over the third metal layer, where the fourth metal layer is aligned to the first metal layer with less than 40 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm.

A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.