A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

A portion of a source electrode exposed by an opening in a passivation film is used as a portion of a source pad. A first portion of the source pad includes a plating film formed by a material that is harder than a material of the source electrode. During screening, a probe needle that is a metal contact contacts the plating film that is on the first portion of the source pad. A second portion of the source pad has a layer structure different from that of the first portion of the source pad and in a second direction parallel to the front surface of the semiconductor chip, is disposed adjacently to and electrically connected to the first portion of the source pad. A bonding wire is wire bonded to the second portion of the source pad after an inspection process of the semiconductor chip.

A portion of a source electrode exposed by an opening in a passivation film is used as a portion of a source pad. A first portion of the source pad includes a plating film formed by a material that is harder than a material of the source electrode. During screening, a probe needle that is a metal contact contacts the plating film that is on the first portion of the source pad. A second portion of the source pad has a layer structure different from that of the first portion of the source pad and in a second direction parallel to the front surface of the semiconductor chip, is disposed adjacently to and electrically connected to the first portion of the source pad. A bonding wire is wire bonded to the second portion of the source pad after an inspection process of the semiconductor chip.

An electronic device according to a present disclosure includes a semiconductor substrate, a chip, and a connection part. The chip has a different thermal expansion rate from that of the semiconductor substrate. The connection part includes a porous metal layer for connecting connection pads that are arranged on opposing principle surfaces of the semiconductor substrate and the chip.

An electronic device according to a present disclosure includes a semiconductor substrate, a chip, and a connection part. The chip has a different thermal expansion rate from that of the semiconductor substrate. The connection part includes a porous metal layer for connecting connection pads that are arranged on opposing principle surfaces of the semiconductor substrate and the chip.

An electronic device according to a present disclosure includes a semiconductor substrate, a chip, and a connection part. The chip has a different thermal expansion rate from that of the semiconductor substrate. The connection part includes a porous metal layer for connecting connection pads that are arranged on opposing principle surfaces of the semiconductor substrate and the chip.

An electronic device according to a present disclosure includes a semiconductor substrate, a chip, and a connection part. The chip has a different thermal expansion rate from that of the semiconductor substrate. The connection part includes a porous metal layer for connecting connection pads that are arranged on opposing principle surfaces of the semiconductor substrate and the chip.

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.