There is provided an Ag alloy bonding wire for semiconductor devices which exhibits a favorable bond reliability in a high-temperature environment even when using a mold resin of high S content and can suppress a chip damage at the time of ball bonding. The Ag alloy bonding wire is characterized by containing at least one element selected from the group consisting of Pd and Pt (hereinafter referred to as a “first element”) and at least one element selected from the group consisting of P, Cr, Zr and Mo (hereinafter referred to as a “second element”) so as to satisfy

[00001]$0.05\le \text{x}1\le 3.0,\text{and}$

[00002]$15\le \text{x}2\le 700$

where x1 is a total concentration of the first element [at.%] and x2 is a total concentration of the second element [at. ppm], with the balance including Ag.

There is provided an Ag alloy bonding wire for semiconductor devices which exhibits a favorable bond reliability in a high-temperature environment even when using a mold resin of high S content and can suppress a chip damage at the time of ball bonding. The Ag alloy bonding wire is characterized by containing at least one element selected from the group consisting of Pd and Pt (hereinafter referred to as a “first element”) and at least one element selected from the group consisting of P, Cr, Zr and Mo (hereinafter referred to as a “second element”) so as to satisfy

[00001]$0.05\le \text{x}1\le 3.0,\text{and}$

[00002]$15\le \text{x}2\le 700$

where x1 is a total concentration of the first element [at.%] and x2 is a total concentration of the second element [at. ppm], with the balance including Ag.

There is provided an Al bonding wire which can achieve a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the Al bonding wire is operated. The Al bonding wire contains 0.01 to 1% of Sc, and further contains 0.01 to 0.1% in total of at least one or more of Y, La, Ce, Pr and Nd. With regard to the Al bonding wire, a recrystallization temperature thereof is increased, so that the proceeding of recrystallization of the bonding wire can be suppressed, and strength of the wire can be prevented from being decreased even when the semiconductor device is continuously used under a high temperature environment. Accordingly, the Al bonding wire can sufficiently secure the reliability of the bonded parts after a high-temperature long-term hysteresis.

There is provided an Al bonding wire which can achieve a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the Al bonding wire is operated. The Al bonding wire contains 0.01 to 1% of Sc, and further contains 0.01 to 0.1% in total of at least one or more of Y, La, Ce, Pr and Nd. With regard to the Al bonding wire, a recrystallization temperature thereof is increased, so that the proceeding of recrystallization of the bonding wire can be suppressed, and strength of the wire can be prevented from being decreased even when the semiconductor device is continuously used under a high temperature environment. Accordingly, the Al bonding wire can sufficiently secure the reliability of the bonded parts after a high-temperature long-term hysteresis.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

A semiconductor device includes a plurality of islands, each having an outer surface including an upper surface and end surfaces, semiconductor chips, above the respective islands, a bonding material, between the islands and the semiconductor chips, and plating layers, formed on the outer surfaces of the islands, and with at least one of the plurality of islands, the island is exposed as a bare surface region at a first end surface, which, among the end surfaces of the one island, faces the island adjacent thereto.

A semiconductor device includes a plurality of islands, each having an outer surface including an upper surface and end surfaces, semiconductor chips, above the respective islands, a bonding material, between the islands and the semiconductor chips, and plating layers, formed on the outer surfaces of the islands, and with at least one of the plurality of islands, the island is exposed as a bare surface region at a first end surface, which, among the end surfaces of the one island, faces the island adjacent thereto.

A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to cover the wiring layer and having a pad opening exposing a portion of the wiring layer as a pad, a front surface protection film formed on the insulating film and being constituted of an insulating material differing from the insulating film and having a second pad opening securing exposure of at least a portion of the pad, a seed layer formed on the pad, and a plating layer formed on the seed layer.

A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to cover the wiring layer and having a pad opening exposing a portion of the wiring layer as a pad, a front surface protection film formed on the insulating film and being constituted of an insulating material differing from the insulating film and having a second pad opening securing exposure of at least a portion of the pad, a seed layer formed on the pad, and a plating layer formed on the seed layer.