An imaging device is provided. The imaging device includes a semiconductor substrate; a first electrode disposed above the semiconductor substrate; a second electrode disposed above the first electrode; and a photoelectric conversion layer disposed between the first electrode and the second electrode, wherein a difference between a work function value of the first electrode and a work function value of the second electrode is 0.4 eV or more, and wherein the first electrode has a sheet resistance value of 3×10 Ω/□ to 1×10.sup.3Ω/□.

There is provided a palladium-coated copper bonding wire that does not cause a shrinkage cavity during first bonding, has high bonding reliability, and is capable of maintaining excellent bonding reliability for a long period of time even in high-temperature and high-humidity environments. A palladium-coated copper bonding wire in which a concentration of palladium is 1.0 mass % or more and 4.0 mass % or less relative to the total of copper, palladium, and a sulfur group element, a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of sulfur is 5 mass ppm or more and 12 mass ppm or less, a concentration of selenium is 5 mass ppm or more and 20 mass ppm or less, or a concentration of tellurium is 15 mass ppm or more and 50 mass ppm or less, and the palladium-coated copper bonding wire including a palladium-concentrated region with the average concentration of palladium of 6.5 atom % or more and 30.0 atom % or less relative to the total of copper and palladium within a range from a surface of a tip portion of a free air ball formed at a tip of the wire to 5.0 nm or more and 100.0 nm or less.

There is provided a palladium-coated copper bonding wire that does not cause a shrinkage cavity during first bonding, has high bonding reliability, and is capable of maintaining excellent bonding reliability for a long period of time even in high-temperature and high-humidity environments. A palladium-coated copper bonding wire in which a concentration of palladium is 1.0 mass % or more and 4.0 mass % or less relative to the total of copper, palladium, and a sulfur group element, a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of sulfur is 5 mass ppm or more and 12 mass ppm or less, a concentration of selenium is 5 mass ppm or more and 20 mass ppm or less, or a concentration of tellurium is 15 mass ppm or more and 50 mass ppm or less, and the palladium-coated copper bonding wire including a palladium-concentrated region with the average concentration of palladium of 6.5 atom % or more and 30.0 atom % or less relative to the total of copper and palladium within a range from a surface of a tip portion of a free air ball formed at a tip of the wire to 5.0 nm or more and 100.0 nm or less.

An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

An object of the present disclosure is to provide a high strength aluminum alloy material having a ribbon shape, which can be an alternative to copper-based materials and iron-based materials having a ribbon shape, and a conductive member, a conductive component, a spring member, a spring component, a semiconductor module member, a semiconductor module component, a structural member and a structural component including the aluminum alloy material. The aluminum alloy material of the present disclosure has an alloy composition containing Mg: 0.2% to 1.8% by mass, Si: 0.2% to 2.0% by mass, and Fe: 0.01% to 1.50% by mass, with the balance being Al and inevitable impurities, wherein the aluminum alloy material has a Vickers hardness (HV) of 90 or more and 190 or less and has a ribbon shape.

An aluminum wire with which, at the time of bonding a bonding wire for a power semiconductor, the wire is not detached from a wedge tool, and a long life is achieved in a power cycle test. The aluminum wire is made of an aluminum alloy having an aluminum purity of 99 mass % or more and contains, relative to a total amount of all elements of the aluminum alloy, a total of 0.01 mass % or more and 1 mass % or less of iron and silicon. In a lateral cross-section in a direction perpendicular to a wire axis of the aluminum wire, an orientation index of is 1 or more, an orientation index of is 1 or less, and an area ratio of precipitated particles is in a range of 0.02% or more to 2% or less.

An electronic device is provided and includes a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode, the first electrode including an amorphous oxide including a quaternary compound including one or more of indium, gallium and aluminum and further including zinc and oxygen, the first electrode having a laminated structure including a first B layer and a first A layer from a photoelectric conversion layer side, and a work function value of the first A layer of the first electrode being lower than a work function of the first B layer of the first electrode.

This invention provides a carrier or submount for high power devices packaging and a method for forming the carrier or submount. The carrier comprises a thermal conductive ceramic substrate with at least one recess region, a patterned adhesion layer on the substrate, a heat dissipation layer on the patterned adhesion layer, a conformal cover layer enclosing the heat dissipation layer and the adhesion layer, a diffusion barrier layer on the conformal cover layer, and an eutectic bonding layer on the diffusion barrier layer. The substrate includes a first region for bonding high power device, a second region for wire-bonding, and a third region for heat sink. The first region and second region are on a first surface of the substrate, and the third region is one the second surface, opposite to the first surface, of the substrate.

A method of manufacturing a semiconductor device of the present disclosure includes the steps of sequentially forming an adhesion-improving film, a Pt film, a Sn film, and an Au film on a semiconductor wafer through vapor deposition; dicing the semiconductor wafer to obtain a semiconductor element; sequentially forming a Ni film and an Au film on a substrate through vapor deposition; and laminating the semiconductor element and the substrate so that the Au film formed on the semiconductor element and the Au film formed on the substrate face each other, followed by joining the semiconductor element and the substrate through heating.