A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting pad under the ceramic base and coupled to the semiconductor die through at least one opening in the ceramic base. The mounting pad includes at least one layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of the ceramic base. The mounting pad includes at least one layer having a low-yield strength of equal to or less than 200 MPa. The mounting pad includes at least one copper layer and at least one molybdenum layer. The semiconductor package also includes a bond pad coupled to another mounting pad under the ceramic base through a conductive slug in the ceramic base.

A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.

The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

A semiconductor device includes an insulating support member, a first and a second conductive layer, a first semiconductor element, a first lead, a first detection conductor and a first gate conductor. The first and second conductive layers are disposed on a front surface of the insulating support member. The first semiconductor includes a first and a second electrode on the same side, and a third electrode disposed on the other side and electrically connected to the first conductive layer. The first lead is connected to the first and second conductive layer. The first detection conductor is connected to the first electrode. The first gate conductor is connected to the second electrode. At least one of the first detection conductor and the first gate conductor has an end connected to the first semiconductor element. The end has a coefficient of linear expansion smaller than that of the first conductive layer.

A semiconductor device includes an insulating support member, a first and a second conductive layer, a first semiconductor element, a first lead, a first detection conductor and a first gate conductor. The first and second conductive layers are disposed on a front surface of the insulating support member. The first semiconductor includes a first and a second electrode on the same side, and a third electrode disposed on the other side and electrically connected to the first conductive layer. The first lead is connected to the first and second conductive layer. The first detection conductor is connected to the first electrode. The first gate conductor is connected to the second electrode. At least one of the first detection conductor and the first gate conductor has an end connected to the first semiconductor element. The end has a coefficient of linear expansion smaller than that of the first conductive layer.