According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first electrode extending in a first direction through the semiconductor substrate between the first surface and the second surface, a first wiring layer on the first surface and electrically connected to the first electrode, and a second wiring layer on the first wiring layer, the first wiring layer being between the semiconductor substrate and the second wiring layer in the first direction. The second wiring layer includes a connection region at which a second electrode is connected and a first air gap between the connection region and an outer edge of the second wiring layer in a second direction crossing the first direction.

According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first electrode extending in a first direction through the semiconductor substrate between the first surface and the second surface, a first wiring layer on the first surface and electrically connected to the first electrode, and a second wiring layer on the first wiring layer, the first wiring layer being between the semiconductor substrate and the second wiring layer in the first direction. The second wiring layer includes a connection region at which a second electrode is connected and a first air gap between the connection region and an outer edge of the second wiring layer in a second direction crossing the first direction.

A method includes providing first and second wafers; forming a first device layer in a top portion of the first wafer; forming a second device layer in a top portion of the second wafer; forming a first groove in the first device layer; forming a second groove in the second device layer; bonding the first and second wafers together after at least one of the first and second grooves is formed; and dicing the bonded first and second wafers by a cutting process, wherein the cutting process cuts through the first and second grooves.

A method includes providing first and second wafers; forming a first device layer in a top portion of the first wafer; forming a second device layer in a top portion of the second wafer; forming a first groove in the first device layer; forming a second groove in the second device layer; bonding the first and second wafers together after at least one of the first and second grooves is formed; and dicing the bonded first and second wafers by a cutting process, wherein the cutting process cuts through the first and second grooves.

A semiconductor element includes a semiconductor substrate; a collector layer on the semiconductor substrate; a base layer on the collector layer; an emitter layer on the base layer; emitter wiring electrically coupled to the emitter layer; a top metal layer on the emitter wiring; a first protective film covering the emitter wiring and the top metal layer, the first protective film having a first opening that overlaps at least the collector layer; and a bump including an under-bump metal layer electrically coupled to the emitter wiring via the first opening, the under-bump metal layer being larger than the first opening in plan-view area. The first protective film has an inner edge around the first opening, and the inner edge is on the top metal layer.

A semiconductor element includes a semiconductor substrate; a collector layer on the semiconductor substrate; a base layer on the collector layer; an emitter layer on the base layer; emitter wiring electrically coupled to the emitter layer; a top metal layer on the emitter wiring; a first protective film covering the emitter wiring and the top metal layer, the first protective film having a first opening that overlaps at least the collector layer; and a bump including an under-bump metal layer electrically coupled to the emitter wiring via the first opening, the under-bump metal layer being larger than the first opening in plan-view area. The first protective film has an inner edge around the first opening, and the inner edge is on the top metal layer.

A method of forming a three dimensional semiconductor structure includes: forming a through dielectric via extending on a first surface of a first interlayer dielectric layer of a first device; bonding the first device and a second device by the first surface and a second surface of the second device such that a through silicon contact pad on the second surface covers the through dielectric via; performing an etching process on a back side of a first substrate of the first device opposite to the first interlayer dielectric layer to simultaneously form a first via hole and a second via hole and exposing the second via hole through the through silicon contact pad; and forming a first via plug to fill the first via hole, and a second via plug to fill the second via hole and the through dielectric via.

A method of forming a three dimensional semiconductor structure includes: forming a through dielectric via extending on a first surface of a first interlayer dielectric layer of a first device; bonding the first device and a second device by the first surface and a second surface of the second device such that a through silicon contact pad on the second surface covers the through dielectric via; performing an etching process on a back side of a first substrate of the first device opposite to the first interlayer dielectric layer to simultaneously form a first via hole and a second via hole and exposing the second via hole through the through silicon contact pad; and forming a first via plug to fill the first via hole, and a second via plug to fill the second via hole and the through dielectric via.

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.