A power semiconductor device is proposed. The power semiconductor device includes a semiconductor substrate. The power semiconductor device further includes an electrically conducting first layer. At least part of the electrically conducting first layer includes pores. The power semiconductor device further includes an electrically conducting second layer. The electrically conducting second layer is arranged between the semiconductor substrate and the electrically conducting first layer. The pores are at least partially filled with a phase change material.

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having first and second sides; forming at least one doping region at the first side; forming a first metallization structure at the first side on and in contact with the at least one doping region; and subsequently forming a second metallization structure at the second side, the second metallization structure forming at least one silicide interface region with the semiconductor substrate and at least one non-silicide interface region with the semiconductor substrate.

A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having first and second sides; forming at least one doping region at the first side; forming a first metallization structure at the first side on and in contact with the at least one doping region; and subsequently forming a second metallization structure at the second side, the second metallization structure forming at least one silicide interface region with the semiconductor substrate and at least one non-silicide interface region with the semiconductor substrate.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed above a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. The first bonding contact is made of a first indiffusible conductive material. A second device layer is formed above a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, such that the first bonding contact is in contact with the second bonding contact at a bonding interface.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed above a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. The first bonding contact is made of a first indiffusible conductive material. A second device layer is formed above a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, such that the first bonding contact is in contact with the second bonding contact at a bonding interface.

In a transistor region of an active region, trench-gate MOS gates for a vertical MOSFET are formed on the front surface side of a semiconductor substrate. In a non-effective/pad region of the active region, a gate pad is formed on the front surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. An n-type region is formed spanning across the entire non-effective region in the surface layer of the front surface of the semiconductor substrate. The portion directly beneath the gate pad is only an n-type region constituted by an n.sup.+ starting substrate, an n.sup. drift region, and the n-type region, with the interlayer insulating film sandwiched thereabove. No n.sup.+ source region is formed in a p-type base region extension which is the portion of a p-type base region that extends into the non-effective region.

In a transistor region of an active region, trench-gate MOS gates for a vertical MOSFET are formed on the front surface side of a semiconductor substrate. In a non-effective/pad region of the active region, a gate pad is formed on the front surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. An n-type region is formed spanning across the entire non-effective region in the surface layer of the front surface of the semiconductor substrate. The portion directly beneath the gate pad is only an n-type region constituted by an n.sup.+ starting substrate, an n.sup. drift region, and the n-type region, with the interlayer insulating film sandwiched thereabove. No n.sup.+ source region is formed in a p-type base region extension which is the portion of a p-type base region that extends into the non-effective region.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact or the second bonding contact is made of an indiffusible conductive material.