Patent classifications
H01L2924/0495
Liquid ejection head substrate and semiconductor substrate
A liquid ejection head substrate includes an electrode pad for receiving driving power for liquid ejection from an outside, the electrode pad including at least a conductor layer and a layer of gold. A portion of the conductor layer has an opening region, and an upper layer portion in a laminating direction above the conductor layer including the opening region has at least the layer of gold. An external connection portion connected to the outside is provided on top of the layer of gold corresponding to the opening region of the conductor layer.
Liquid ejection head substrate and semiconductor substrate
A liquid ejection head substrate includes an electrode pad for receiving driving power for liquid ejection from an outside, the electrode pad including at least a conductor layer and a layer of gold. A portion of the conductor layer has an opening region, and an upper layer portion in a laminating direction above the conductor layer including the opening region has at least the layer of gold. An external connection portion connected to the outside is provided on top of the layer of gold corresponding to the opening region of the conductor layer.
Cryogenic electronic packages and methods for fabricating cryogenic electronic packages
A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.
Cryogenic electronic packages and methods for fabricating cryogenic electronic packages
A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.
BOND PADS WITH SURROUNDING FILL LINES
Bond pad structures and methods for fabricating bond pad structures. A bond pad and a plurality of fill lines are formed on the top surface of a dielectric layer. The fill lines are arranged on the top surface of the dielectric layer adjacent to the bond pad, and may be separated from the bond pad by a fill keep-out zone. One or more Under Bump Metallurgy (UBM) layers may be arranged on the bond pad and may extend outwardly to overlap with the fill lines.
BOND PADS WITH SURROUNDING FILL LINES
Bond pad structures and methods for fabricating bond pad structures. A bond pad and a plurality of fill lines are formed on the top surface of a dielectric layer. The fill lines are arranged on the top surface of the dielectric layer adjacent to the bond pad, and may be separated from the bond pad by a fill keep-out zone. One or more Under Bump Metallurgy (UBM) layers may be arranged on the bond pad and may extend outwardly to overlap with the fill lines.
Methods of forming a microelectronic device structure, and related microelectronic device structures and microelectronic devices
A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.
Methods of forming a microelectronic device structure, and related microelectronic device structures and microelectronic devices
A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.
LIQUID EJECTION HEAD SUBSTRATE AND SEMICONDUCTOR SUBSTRATE
A liquid ejection head substrate includes an electrode pad for receiving driving power for liquid ejection from an outside, the electrode pad including at least a conductor layer and a layer of gold. A portion of the conductor layer has an opening region, and an upper layer portion in a laminating direction above the conductor layer including the opening region has at least the layer of gold. An external connection portion connected to the outside is provided on top of the layer of gold corresponding to the opening region of the conductor layer.
LIQUID EJECTION HEAD SUBSTRATE AND SEMICONDUCTOR SUBSTRATE
A liquid ejection head substrate includes an electrode pad for receiving driving power for liquid ejection from an outside, the electrode pad including at least a conductor layer and a layer of gold. A portion of the conductor layer has an opening region, and an upper layer portion in a laminating direction above the conductor layer including the opening region has at least the layer of gold. An external connection portion connected to the outside is provided on top of the layer of gold corresponding to the opening region of the conductor layer.