Patent classifications
H01L2924/0534
COAXIAL WIRE
A micro-coaxial wire has an overall diameter in a range of 0.1 m-550 m, a conductive core of the wire has a cross-sectional diameter in a range of 0.05 m-304 m, an insulator is disposed on the conductive core with thickness in a range of 0.005 m-180 m, and a conductive shield layer is disposed on the insulator with thickness in a range of 0.009 m-99 m.
Methods of forming a microelectronic device
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.
Methods of forming a microelectronic device
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.
CURABLE ORGANOPOLYSILOXANE COMPOSITION AND SEMICONDUCTOR DEVICE
The present invention pertains to a curable organopolysiloxane composition comprising at least (A) an organopolysiloxane having at least two alkenyl groups per module, (B) an organopolysiloxane resin represented by average unit formula: (R.sup.1.sub.3SiO.sub.1/2).sub.a(R.sup.1.sub.2SiO.sub.2/2).sub.b(R.sup.2SiO.sub.3/2).sub.c(SiO.sub.4/2).sub.d. In the formula, R.sup.1's are the same or different from each other, and represent a hydrogen atom or a monovalent hydrocarbon group not having an aliphatic unsaturated carbon bond but at least two of the R.sup.1's per molecule represent hydrogen atoms, R.sup.2 represents a monovalent hydrocarbon group not having an aliphatic unsaturated bond, and a, b, and c are numbers satisfying 0<a<1, 0<b<1, and 0c0.2, and 0<d<1, respectively, but are also numbers satisfying 0.6a/d 1.5, 1.5b/d3, and a+b+c+d=1, and (C) a catalyst for hydrosilylation reaction. This composition has excellent adhesiveness to a semiconductor element, and can form a cured product in which only a small number of bubbles are produced.
CURABLE ORGANOPOLYSILOXANE COMPOSITION AND SEMICONDUCTOR DEVICE
The present invention pertains to a curable organopolysiloxane composition comprising at least (A) an organopolysiloxane having at least two alkenyl groups per module, (B) an organopolysiloxane resin represented by average unit formula: (R.sup.1.sub.3SiO.sub.1/2).sub.a(R.sup.1.sub.2SiO.sub.2/2).sub.b(R.sup.2SiO.sub.3/2).sub.c(SiO.sub.4/2).sub.d. In the formula, R.sup.1's are the same or different from each other, and represent a hydrogen atom or a monovalent hydrocarbon group not having an aliphatic unsaturated carbon bond but at least two of the R.sup.1's per molecule represent hydrogen atoms, R.sup.2 represents a monovalent hydrocarbon group not having an aliphatic unsaturated bond, and a, b, and c are numbers satisfying 0<a<1, 0<b<1, and 0c0.2, and 0<d<1, respectively, but are also numbers satisfying 0.6a/d 1.5, 1.5b/d3, and a+b+c+d=1, and (C) a catalyst for hydrosilylation reaction. This composition has excellent adhesiveness to a semiconductor element, and can form a cured product in which only a small number of bubbles are produced.
ADHESIVE FILM FOR SEMICONDUCTOR, AND SEMICONDUCTOR DEVICE
There are provided an adhesive film for a semiconductor including: a conductive layer containing at least one metal selected from the group consisting of copper, nickel, cobalt, iron, stainless steel (SUS), and aluminum, and having a thickness of 0.05 m or more; and an adhesive layer formed on at least one surface of the conductive layer and including a (meth)acrylate-based resin, a curing agent, and an epoxy resin, and a semiconductor device including the above-mentioned adhesive film.
ADHESIVE FILM FOR SEMICONDUCTOR, AND SEMICONDUCTOR DEVICE
There are provided an adhesive film for a semiconductor including: a conductive layer containing at least one metal selected from the group consisting of copper, nickel, cobalt, iron, stainless steel (SUS), and aluminum, and having a thickness of 0.05 m or more; and an adhesive layer formed on at least one surface of the conductive layer and including a (meth)acrylate-based resin, a curing agent, and an epoxy resin, and a semiconductor device including the above-mentioned adhesive film.
DRY ETCH PROCESS LANDING ON METAL OXIDE ETCH STOP LAYER OVER METAL LAYER AND STRUCTURE FORMED THEREBY
A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.
STACKED SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
A stacked semiconductor device is provided, including a first semiconductor structure, a second semiconductor structure and a bonding structure disposed between the first and second semiconductor structures. The first semiconductor structure and the second semiconductor structure include first conductive pillars and second conductive pillars, respectively. The first semiconductor structure is stacked above the second semiconductor structure. The bonding structure contacts the first conductive pillars and the second conductive pillars, wherein the bonding structure comprises conductive paths for electrically connecting the first conductive pillars and the second conductive pillars.
STACKED SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
A stacked semiconductor device is provided, including a first semiconductor structure, a second semiconductor structure and a bonding structure disposed between the first and second semiconductor structures. The first semiconductor structure and the second semiconductor structure include first conductive pillars and second conductive pillars, respectively. The first semiconductor structure is stacked above the second semiconductor structure. The bonding structure contacts the first conductive pillars and the second conductive pillars, wherein the bonding structure comprises conductive paths for electrically connecting the first conductive pillars and the second conductive pillars.