A display panel measures a contact resistance of an adhesive portion to evaluate adhesion quality of an integrated circuit mounted thereon. The display panel includes a plurality of light-emitting elements, a first pad part including a plurality of first effective pads electrically connected to the light-emitting elements, and n (n being a natural number equal to or greater than 2) first measuring pads insulated from the light-emitting elements, a conductive adhesive film on the first pad part and including a plurality of conductive balls, an integrated circuit on the conductive adhesive film, and including an internal line electrically connected to the first measuring pads by the conductive balls, and a second pad part including a plurality of second effective pads electrically connected to the first effective pads, and 2n second measuring pads electrically connected to the first measuring pads.

A display panel measures a contact resistance of an adhesive portion to evaluate adhesion quality of an integrated circuit mounted thereon. The display panel includes a plurality of light-emitting elements, a first pad part including a plurality of first effective pads electrically connected to the light-emitting elements, and n (n being a natural number equal to or greater than 2) first measuring pads insulated from the light-emitting elements, a conductive adhesive film on the first pad part and including a plurality of conductive balls, an integrated circuit on the conductive adhesive film, and including an internal line electrically connected to the first measuring pads by the conductive balls, and a second pad part including a plurality of second effective pads electrically connected to the first effective pads, and 2n second measuring pads electrically connected to the first measuring pads.

Discloses is a method of bonding a semiconductor device, for example, a sintering bonding method for a semiconductor device that can mix pure particles and copper (I) oxide nano particles on a metal substrate. The paste of the present invention may provide low-cost copper paste increasing a copper density as a bonding material when bonding a semiconductor chip continuously used at a high temperature. The copper paste of the present invention may suppress the occurrence of pores or cracks when sintering by heating the copper paste under the reduction atmosphere as saving material costs and implementing an optimum high heat-resistance bonding.

Discloses is a method of bonding a semiconductor device, for example, a sintering bonding method for a semiconductor device that can mix pure particles and copper (I) oxide nano particles on a metal substrate. The paste of the present invention may provide low-cost copper paste increasing a copper density as a bonding material when bonding a semiconductor chip continuously used at a high temperature. The copper paste of the present invention may suppress the occurrence of pores or cracks when sintering by heating the copper paste under the reduction atmosphere as saving material costs and implementing an optimum high heat-resistance bonding.

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

A display panel measures a contact resistance of an adhesive portion to evaluate adhesion quality of an integrated circuit mounted thereon. The display panel includes a plurality of light-emitting elements, a first pad part including a plurality of first effective pads electrically connected to the light-emitting elements, and n (n being a natural number equal to or greater than 2) first measuring pads insulated from the light-emitting elements, a conductive adhesive film on the first pad part and including a plurality of conductive balls, an integrated circuit on the conductive adhesive film, and including an internal line electrically connected to the first measuring pads by the conductive balls, and a second pad part including a plurality of second effective pads electrically connected to the first effective pads, and 2n second measuring pads electrically connected to the first measuring pads.

A display panel measures a contact resistance of an adhesive portion to evaluate adhesion quality of an integrated circuit mounted thereon. The display panel includes a plurality of light-emitting elements, a first pad part including a plurality of first effective pads electrically connected to the light-emitting elements, and n (n being a natural number equal to or greater than 2) first measuring pads insulated from the light-emitting elements, a conductive adhesive film on the first pad part and including a plurality of conductive balls, an integrated circuit on the conductive adhesive film, and including an internal line electrically connected to the first measuring pads by the conductive balls, and a second pad part including a plurality of second effective pads electrically connected to the first effective pads, and 2n second measuring pads electrically connected to the first measuring pads.

An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.