H01L2924/0545

WAFER LEVEL PACKAGE STRUCTURE AND WAFER LEVEL PACKAGING METHOD
20200075539 · 2020-03-05 ·

Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process.

Rare earth pnictides for strain management
10332857 · 2019-06-25 · ·

Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more Group V elements. In some examples, the desired strain is approximately zero.

Pnictide Buffer Structures and Devices for GaN Base Applications
20190139761 · 2019-05-09 ·

A structure can include a III-N layer with a first lattice constant, a first rare earth pnictide layer with a second lattice constant epitaxially grown over the III-N layer, a second rare earth pnictide layer with a third lattice constant epitaxially grown over the first rare earth pnictide layer, and a semiconductor layer with a fourth lattice constant epitaxially grown over the second rare earth pnictide layer. A first difference between the first lattice constant and the second lattice constant and a second difference between the third lattice constant and the fourth lattice constant are less than one percent.

Solder thermal interface material (STIM) with dopant

Embodiments may relate to a microelectronic package comprising that includes a solder thermal interface material (STIM). The STIM may include indium and a dopant material which may provide a number of benefits to the STIM. The STIM may physically and thermally couple a die and an integrated heat spreader (IHS). Other embodiments may be described or claimed.

Solder thermal interface material (STIM) with dopant

Embodiments may relate to a microelectronic package comprising that includes a solder thermal interface material (STIM). The STIM may include indium and a dopant material which may provide a number of benefits to the STIM. The STIM may physically and thermally couple a die and an integrated heat spreader (IHS). Other embodiments may be described or claimed.

IMPROVED ADHESIVE BONDING COMPOSITION AND METHOD OF USE

A method of and system for adhesive bonding. The method and system a) treat a surface of an element to be bonded to provide an adherent structure including one or more rubber compounds on the surface; b) place a polymerizable adhesive composition, including at least one photoinitiator and at least one energy converting material, in contact with the adherent structure and two or more components to be bonded to form an assembly, c) irradiated the assembly with radiation at a first wavelength, capable of conversion by the at least one energy converting material, to a second wavelength capable of activating the at least one photoinitiator to produce from the polymerizable adhesive composition a cured adhesive composition; and d) adhesively join the two or more components by way of the adherent structure and the cured adhesive composition.

IMPROVED ADHESIVE BONDING COMPOSITION AND METHOD OF USE

A method of and system for adhesive bonding. The method and system a) treat a surface of an element to be bonded to provide an adherent structure including one or more rubber compounds on the surface; b) place a polymerizable adhesive composition, including at least one photoinitiator and at least one energy converting material, in contact with the adherent structure and two or more components to be bonded to form an assembly, c) irradiated the assembly with radiation at a first wavelength, capable of conversion by the at least one energy converting material, to a second wavelength capable of activating the at least one photoinitiator to produce from the polymerizable adhesive composition a cured adhesive composition; and d) adhesively join the two or more components by way of the adherent structure and the cured adhesive composition.

HIGH CAPACITANCE HYBRID BONDED CAPACITOR DEVICE

Techniques are provided for hybrid bonding metallic bonding pads embedded in high-K dielectric material to form a high capacitance device. For example, a device comprises a first semiconductor structure bonded to a second semiconductor structure, and a plurality of metal pads at an interface portion between the first semiconductor structure and the second semiconductor structure. The plurality of metal pads are disposed in a high-K dielectric layer. The plurality of metal pads and the high-K dielectric layer comprise at least one capacitor.

STACKED HIGH-POWER RF SWITCH
20250323228 · 2025-10-16 ·

The present disclosure relates to semiconductor structures and, more particularly, to a stacked high-power radio frequency (RF) switch and methods of manufacture. The structure includes: a top substrate having at least one top transistor and metal wiring structures; and a bottom substrate having at least one bottom transistor and metal wiring structure. The bottom substrate is attached to the top substrate with the at least one top transistor being electrically connected to the at least one bottom transistor. A portion of the metal wiring structures of the top substrate and a portion of the metal wiring structures of the bottom substrate being at least one shared capacitor between the at least one top transistor and the at least one bottom transistor. Airgaps may be formed above the transistor.