A semiconductor package includes a circuit board mounting a first semiconductor chip and a second semiconductor chip laterally separated by an intermediate space, an underfill including an extended portion protruding upward into the intermediate space, a surface modification layer on opposing side surfaces of the first semiconductor chip and the second semiconductor chip, wherein wettability of the underfill with respect to the surface modification layer is less than wettability of the underfill with respect to the side surfaces of the first semiconductor chip and the second semiconductor chip, and a molding member on the upper surface of the circuit board, covering an upper surface of the extended portion of the underfill, and surrounding the first semiconductor chip and the second semiconductor chip.

A semiconductor package includes a circuit board mounting a first semiconductor chip and a second semiconductor chip laterally separated by an intermediate space, an underfill including an extended portion protruding upward into the intermediate space, a surface modification layer on opposing side surfaces of the first semiconductor chip and the second semiconductor chip, wherein wettability of the underfill with respect to the surface modification layer is less than wettability of the underfill with respect to the side surfaces of the first semiconductor chip and the second semiconductor chip, and a molding member on the upper surface of the circuit board, covering an upper surface of the extended portion of the underfill, and surrounding the first semiconductor chip and the second semiconductor chip.

A method for forming a chip package structure is provided. The method includes disposing a chip package over a wiring substrate. The method includes forming a first heat conductive structure and a second heat conductive structure over the chip package. The first heat conductive structure and the second heat conductive structure are separated by a first gap. The method includes bonding a heat dissipation lid to the chip package through the first heat conductive structure and the second heat conductive structure. The first heat conductive structure and the second heat conductive structure extend toward each other until the first heat conductive structure contacts the second heat conductive structure during bonding the heat dissipation lid to the chip package.

A method for forming a chip package structure is provided. The method includes disposing a chip package over a wiring substrate. The method includes forming a first heat conductive structure and a second heat conductive structure over the chip package. The first heat conductive structure and the second heat conductive structure are separated by a first gap. The method includes bonding a heat dissipation lid to the chip package through the first heat conductive structure and the second heat conductive structure. The first heat conductive structure and the second heat conductive structure extend toward each other until the first heat conductive structure contacts the second heat conductive structure during bonding the heat dissipation lid to the chip package.

Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second end, the sixth surface being in contact with the first surface.

Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second end, the sixth surface being in contact with the first surface.

The present disclosure relates to a semiconductor device structure with a conductive polymer liner and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first metal layer disposed over a semiconductor substrate, and a second metal layer disposed over the first metal layer. The semiconductor device structure also includes a conductive structure disposed between the first metal layer and the second metal layer. The conductive structure includes a first conductive via and a first conductive polymer liner surrounding the first conductive via.

The present disclosure relates to a semiconductor device structure with a conductive polymer liner and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first metal layer disposed over a semiconductor substrate, and a second metal layer disposed over the first metal layer. The semiconductor device structure also includes a conductive structure disposed between the first metal layer and the second metal layer. The conductive structure includes a first conductive via and a first conductive polymer liner surrounding the first conductive via.

An electroplating method that is a conventional method has had a problem that it is difficult to manufacture fine pillars without being affected by an undercut. Furthermore, an electroless plating method has had a problem that it is difficult to manufacture pillars having the same shape without any void. The inventors have performed intensive investigations to solve the above problems and, as a result, have found that fine conductive pillars with a high aspect ratio can be readily manufactured on a substrate having an electrode section in such a manner that after a conductive paste containing metal micro-particles is applied in a reduced pressure state, the conductive paste is exposed to standard pressure. The present invention has a particular effect on the manufacture of a metal pillar that is a terminal for flip-chip mounting.

An electroplating method that is a conventional method has had a problem that it is difficult to manufacture fine pillars without being affected by an undercut. Furthermore, an electroless plating method has had a problem that it is difficult to manufacture pillars having the same shape without any void. The inventors have performed intensive investigations to solve the above problems and, as a result, have found that fine conductive pillars with a high aspect ratio can be readily manufactured on a substrate having an electrode section in such a manner that after a conductive paste containing metal micro-particles is applied in a reduced pressure state, the conductive paste is exposed to standard pressure. The present invention has a particular effect on the manufacture of a metal pillar that is a terminal for flip-chip mounting.