H01L2924/0615

SEMICONDUCTOR PACKAGE AND PoP TYPE PACKAGE
20210151411 · 2021-05-20 · ·

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
20210098418 · 2021-04-01 · ·

A manufacturing method includes the step of forming a diced semiconductor wafer (10) including semiconductor chips (11) from a semiconductor wafer (W) typically on a dicing tape (T1). The diced semiconductor wafer (10) on the dicing tape (T1) is laminated with a sinter-bonding sheet (20). The semiconductor chips (11) each with a sinter-bonding material layer (21) derived from the sinter-bonding sheet (20) are picked up typically from the dicing tape (T1). The semiconductor chips (11) each with the sinter-bonding material layer are temporarily secured through the sinter-bonding material layer (21) to a substrate. Through a heating process, sintered layers are formed from the sinter-bonding material layers (21) lying between the temporarily secured semiconductor chips (11) and the substrate, to bond the semiconductor chips (11) to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to individual semiconductor chips while reducing loss of the sinter-bonding material.

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
20210098418 · 2021-04-01 · ·

A manufacturing method includes the step of forming a diced semiconductor wafer (10) including semiconductor chips (11) from a semiconductor wafer (W) typically on a dicing tape (T1). The diced semiconductor wafer (10) on the dicing tape (T1) is laminated with a sinter-bonding sheet (20). The semiconductor chips (11) each with a sinter-bonding material layer (21) derived from the sinter-bonding sheet (20) are picked up typically from the dicing tape (T1). The semiconductor chips (11) each with the sinter-bonding material layer are temporarily secured through the sinter-bonding material layer (21) to a substrate. Through a heating process, sintered layers are formed from the sinter-bonding material layers (21) lying between the temporarily secured semiconductor chips (11) and the substrate, to bond the semiconductor chips (11) to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to individual semiconductor chips while reducing loss of the sinter-bonding material.

Lead-free solder alloy, solder joint, solder paste composition, electronic circuit board, and electronic device

According to one aspect of the present invention, a lead-free solder alloy includes 2% by mass or more and 3.1% by mass or less of Ag, more than 0% by mass and 1% by mass or less of Cu, 1% by mass or more and 5% by mass or less of Sb, 3.1% by mass or more and 4.5% by mass or less of Bi, 0.01% by mass or more and 0.25% by mass or less of Ni, and Sn.

Lead-free solder alloy, solder joint, solder paste composition, electronic circuit board, and electronic device

According to one aspect of the present invention, a lead-free solder alloy includes 2% by mass or more and 3.1% by mass or less of Ag, more than 0% by mass and 1% by mass or less of Cu, 1% by mass or more and 5% by mass or less of Sb, 3.1% by mass or more and 4.5% by mass or less of Bi, 0.01% by mass or more and 0.25% by mass or less of Ni, and Sn.

SEMICONDUCTOR DIE PACKAGE WITH WARPAGE MANAGEMENT AND PROCESS FOR FORMING SUCH
20210066152 · 2021-03-04 ·

A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material

SEMICONDUCTOR DIE PACKAGE WITH WARPAGE MANAGEMENT AND PROCESS FOR FORMING SUCH
20210066152 · 2021-03-04 ·

A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
20210066234 · 2021-03-04 ·

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
20210066234 · 2021-03-04 ·

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

MAGNETIC SHIELDING MATERIAL WITH INSULATOR-COATED FERROMAGNETIC PARTICLES
20210035920 · 2021-02-04 ·

A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.