Patent classifications
H01L2924/063
Lead-free solder alloy, solder joining material, electronic circuit mounting substrate, and electronic control device
A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.
THERMOSETTING SHEET, DICING DIE BONDING FILM, AND SEMICONDUCTOR APPARATUS
Provided in the present invention is a thermosetting sheet including a thermosetting resin, a thermoplastic resin, a volatile component, and conductive particles. The thermosetting sheet has an arithmetic average roughness Ra of 0.1 μm or more and 1.2 μm or less that is measured in a state before being cured.
THERMOSETTING SHEET, DICING DIE BONDING FILM, AND SEMICONDUCTOR APPARATUS
Provided in the present invention is a thermosetting sheet including a thermosetting resin, a thermoplastic resin, a volatile component, and conductive particles. The thermosetting sheet has an arithmetic average roughness Ra of 0.1 μm or more and 1.2 μm or less that is measured in a state before being cured.
Semiconductor package including plurality of semiconductor chips and method for manufacturing the same
A semiconductor package manufacturing method of the disclosure includes providing a multilayer adhesive film, forming a notch and a plurality of openings extending through the multilayer adhesive film, attaching the multilayer adhesive film to a back side of a wafer to form a stack, separating the stack into a plurality of individual stacks, separating each of the plurality of individual stacks into an upper stack and a lower stack, providing a substrate on which a first semiconductor chip is mounted, and stacking the upper stack on the first semiconductor chip. The upper stack includes a second semiconductor chip and a die attach pattern covering a portion of a back surface of the second semiconductor chip. A first side surface of the die attach pattern is aligned with a first side surface of the first semiconductor chip.
Semiconductor package including plurality of semiconductor chips and method for manufacturing the same
A semiconductor package manufacturing method of the disclosure includes providing a multilayer adhesive film, forming a notch and a plurality of openings extending through the multilayer adhesive film, attaching the multilayer adhesive film to a back side of a wafer to form a stack, separating the stack into a plurality of individual stacks, separating each of the plurality of individual stacks into an upper stack and a lower stack, providing a substrate on which a first semiconductor chip is mounted, and stacking the upper stack on the first semiconductor chip. The upper stack includes a second semiconductor chip and a die attach pattern covering a portion of a back surface of the second semiconductor chip. A first side surface of the die attach pattern is aligned with a first side surface of the first semiconductor chip.
PHYSICAL QUANTITY SENSOR AND SEMICONDUCTOR DEVICE
A device includes: a chip; a support member; an adhesive layer disposed on the support member; and a wire electrically connected to the sensor chip on a side face of the sensor chip. Herein the adhesive layer includes a material exhibiting a dilatancy property in which a shear stress increases in a multi-dimensional function as a shear rate increases.
PHYSICAL QUANTITY SENSOR AND SEMICONDUCTOR DEVICE
A device includes: a chip; a support member; an adhesive layer disposed on the support member; and a wire electrically connected to the sensor chip on a side face of the sensor chip. Herein the adhesive layer includes a material exhibiting a dilatancy property in which a shear stress increases in a multi-dimensional function as a shear rate increases.
ADHESIVE COMPOSITION, FILM-LIKE ADHESIVE AND PRODUCTION METHOD THEREOF, AND SEMICONDUCTOR PACKAGE USING FILM-LIKE ADHESIVE AND PRODUCTION METHOD THEREOF
An adhesive composition, containing an epoxy resin (A), an epoxy resin curing agent (B), a polymer component (C) and an inorganic filler (D), in which the inorganic filler (D) satisfies the condition (1) of (an average particle diameter (d50) is 0.1 to 3.5 μm) and condition (2) of (a ratio of a particle diameter at 90% cumulative distribution frequency (d90) to the average particle diameter (d50) is 5.0 or less), and a proportion of the inorganic filler (D) in a total content of the epoxy resin (A), the epoxy resin curing agent (B), the polymer component (C) and the inorganic filler (D) is 20 to 70% by volume; a film-like adhesive and a production method thereof; and a semiconductor package and a production method thereof.
ADHESIVE COMPOSITION, FILM-LIKE ADHESIVE AND PRODUCTION METHOD THEREOF, AND SEMICONDUCTOR PACKAGE USING FILM-LIKE ADHESIVE AND PRODUCTION METHOD THEREOF
An adhesive composition, containing an epoxy resin (A), an epoxy resin curing agent (B), a polymer component (C) and an inorganic filler (D), in which the inorganic filler (D) satisfies the condition (1) of (an average particle diameter (d50) is 0.1 to 3.5 μm) and condition (2) of (a ratio of a particle diameter at 90% cumulative distribution frequency (d90) to the average particle diameter (d50) is 5.0 or less), and a proportion of the inorganic filler (D) in a total content of the epoxy resin (A), the epoxy resin curing agent (B), the polymer component (C) and the inorganic filler (D) is 20 to 70% by volume; a film-like adhesive and a production method thereof; and a semiconductor package and a production method thereof.
LEAD-FREE SOLDER ALLOY, SOLDER JOINING MATERIAL, ELECTRONIC CIRCUIT MOUNTING SUBSTRATE, AND ELECTRONIC CONTROL DEVICE
A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.