H01L2924/066

Package and manufacturing method thereof

A package includes a first die, a second die, an encapsulant, and a redistribution structure. The first die has a first capacitor embedded therein. The second die has a second capacitor embedded therein. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die. The redistribution structure is disposed on the second die and the encapsulant.

Sinter-bonding composition, sinter-bonding sheet and dicing tape with sinter-bonding sheet

The sinter-bonding composition contains sinterable particles containing an electroconductive metal. The average particle diameter of the sinterable particles is 2 μm or less and the proportion of the particles having a particle diameter of 100 nm or less in the sinterable particles is not less than 80% by mass. The sinter-bonding sheet (10) has an adhesive layer made from such a sinter-bonding composition. The dicing tape with a sinter-bonding sheet (X) has such a sinter-bonding sheet (10) and a dicing tape (20). The dicing tape (20) has a lamination structure containing a base material (21) and an adhesive layer (22), and the sinter-bonding sheet (10) is positioned on the adhesive layer (22) of the dicing tape (20).

Sinter-bonding composition, sinter-bonding sheet and dicing tape with sinter-bonding sheet

The sinter-bonding composition contains sinterable particles containing an electroconductive metal. The average particle diameter of the sinterable particles is 2 μm or less and the proportion of the particles having a particle diameter of 100 nm or less in the sinterable particles is not less than 80% by mass. The sinter-bonding sheet (10) has an adhesive layer made from such a sinter-bonding composition. The dicing tape with a sinter-bonding sheet (X) has such a sinter-bonding sheet (10) and a dicing tape (20). The dicing tape (20) has a lamination structure containing a base material (21) and an adhesive layer (22), and the sinter-bonding sheet (10) is positioned on the adhesive layer (22) of the dicing tape (20).

DICING DIE BONDING FILM
20220157637 · 2022-05-19 · ·

A dicing die bonding film according to the present invention includes: a dicing tape including a base layer and an adhesive layer laminated on the base layer; and a die bonding layer laminated on the adhesive layer of the deicing tape; the die bonding layer including a matrix resin, a thiol-group-containing compound, and conductive particles.

DICING DIE BONDING FILM
20220157637 · 2022-05-19 · ·

A dicing die bonding film according to the present invention includes: a dicing tape including a base layer and an adhesive layer laminated on the base layer; and a die bonding layer laminated on the adhesive layer of the deicing tape; the die bonding layer including a matrix resin, a thiol-group-containing compound, and conductive particles.

Semiconductor package
11735542 · 2023-08-22 · ·

A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

Semiconductor package
11735542 · 2023-08-22 · ·

A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

Lead-free solder alloy, solder joining material, electronic circuit mounting substrate, and electronic control device

A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.