Provided is a method for manufacturing a semiconductor package, the method including providing a semiconductor chip on a substrate, providing a bonding member between the substrate and the semiconductor chip, and bonding the semiconductor chip on the substrate by irradiating of a laser on the substrate. Here, the bonding member may include a thermosetting resin, a curing agent, and a laser absorbing agent.

A method comprises: providing a layer of curable adhesive material (4) on a substrate (2); forming a pattern of microstructures (321) on the layer of curable adhesive material (4); curing a first region (42) of the layer of curable adhesive material (4) at a first level and a second region (44) of the layer of curable adhesive material (4) at a second level greater than the first level; providing a solid circuit die (6) to directly attach to a major surface of the first region (42) of the layer of curable adhesive material (4); and further curing the first region (42) of the layer of curable adhesive material (4) to anchor the solid circuit die (6) on the first region (42) by forming an adhesive bond therebetween. The pattern of microstructures (321) may include one or more microchannels (321), the method further comprising forming one or more electrically conductive traces in the microchannels (321), in particular, by flow of a conductive particle containing liquid (8) by a capillary force and, optionally, under pressure. The at least one microchannel (321) may extend from the second region (44) to the first region (42) and have a portion beneath the solid circuit die (6). The solid circuit die (6) may have at least one edge disposed within a periphery of the first region (42) with a gap therebetween. The solid circuit die (6) may have at least one contact pad (72) on a bottom surface thereof, wherein the at least one contact pad (72) may be in direct contact with at least one of the electrically conductive traces in the microchannels (321). Forming the pattern of microstructures (321) may comprise contacting a major surface of a stamp (3) to the layer of curable adhesive material (4), the major surface having a pattern of raised features (32) thereon. The curable adhesive material (4) may be cured by an actinic light source such as an ultraviolet (UV) light source (7, 7′), wherein a mask may be provided to at least partially block the first region (42) of the layer of curable adhesive material (4) from the cure. The stamp (3) may be positioned in contact with the curable adhesive material (4) to replicate the pattern of raised features (32) to form the microstructures (321) while the curable adhesive material (4) is selectively cured by the actinic light source such as the ultraviolet (UV) light source (7). The first region (42) of the layer of curab

A method comprises: providing a layer of curable adhesive material (4) on a substrate (2); forming a pattern of microstructures (321) on the layer of curable adhesive material (4); curing a first region (42) of the layer of curable adhesive material (4) at a first level and a second region (44) of the layer of curable adhesive material (4) at a second level greater than the first level; providing a solid circuit die (6) to directly attach to a major surface of the first region (42) of the layer of curable adhesive material (4); and further curing the first region (42) of the layer of curable adhesive material (4) to anchor the solid circuit die (6) on the first region (42) by forming an adhesive bond therebetween. The pattern of microstructures (321) may include one or more microchannels (321), the method further comprising forming one or more electrically conductive traces in the microchannels (321), in particular, by flow of a conductive particle containing liquid (8) by a capillary force and, optionally, under pressure. The at least one microchannel (321) may extend from the second region (44) to the first region (42) and have a portion beneath the solid circuit die (6). The solid circuit die (6) may have at least one edge disposed within a periphery of the first region (42) with a gap therebetween. The solid circuit die (6) may have at least one contact pad (72) on a bottom surface thereof, wherein the at least one contact pad (72) may be in direct contact with at least one of the electrically conductive traces in the microchannels (321). Forming the pattern of microstructures (321) may comprise contacting a major surface of a stamp (3) to the layer of curable adhesive material (4), the major surface having a pattern of raised features (32) thereon. The curable adhesive material (4) may be cured by an actinic light source such as an ultraviolet (UV) light source (7, 7′), wherein a mask may be provided to at least partially block the first region (42) of the layer of curable adhesive material (4) from the cure. The stamp (3) may be positioned in contact with the curable adhesive material (4) to replicate the pattern of raised features (32) to form the microstructures (321) while the curable adhesive material (4) is selectively cured by the actinic light source such as the ultraviolet (UV) light source (7). The first region (42) of the layer of curab

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

A connection structure including: a first circuit member having a plurality of first electrodes; a second circuit member having a plurality of second electrodes; and an intermediate layer having a plurality of bonding portions electrically connecting the first electrodes and the second electrodes, in which at least one of the first electrode and the second electrode that are connected by the bonding portion is a gold electrode, and 90% or more of the plurality of bonding portions include a first region containing a tin-gold alloy and connecting the first electrode and the second electrode and a second region containing bismuth and being in contact with the first region.

A thermosetting sheet according to the present invention includes a thermosetting resin and a thermoplastic resin, in which a thickness change rate when a temperature is changed from 25° C. to 200° C. is 0% or more and 10% or less.

A thermosetting sheet according to the present invention includes a thermosetting resin and a thermoplastic resin, in which a thickness change rate when a temperature is changed from 25° C. to 200° C. is 0% or more and 10% or less.