A dicing die bonding film according to the present invention includes: a dicing tape including a base layer and an adhesive layer laminated on the base layer; and a die bonding layer laminated on the adhesive layer of the deicing tape; the die bonding layer including a matrix resin, a thiol-group-containing compound, and conductive particles.

A dicing die bonding film according to the present invention includes: a dicing tape including a base layer and an adhesive layer laminated on the base layer; and a die bonding layer laminated on the adhesive layer of the deicing tape; the die bonding layer including a matrix resin, a thiol-group-containing compound, and conductive particles.

A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

Provided in the present invention is a thermosetting sheet including a thermosetting resin, a thermoplastic resin, a volatile component, and conductive particles. The thermosetting sheet has an arithmetic average roughness Ra of 0.1 μm or more and 1.2 μm or less that is measured in a state before being cured.

Provided in the present invention is a thermosetting sheet including a thermosetting resin, a thermoplastic resin, a volatile component, and conductive particles. The thermosetting sheet has an arithmetic average roughness Ra of 0.1 μm or more and 1.2 μm or less that is measured in a state before being cured.

Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second end, the sixth surface being in contact with the first surface.

Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second end, the sixth surface being in contact with the first surface.

An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.

An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.