A packaged electronic device is disclosed, comprising: a package, a die and a first bondwire. The package comprises a leadframe. The leadframe comprises a first conducting leadframe element and a second conducting leadframe element that are separate from each other. The die comprises a first bondpad. The first bondwire electrically connects the first bondpad to the first conducting leadframe element. The die mechanically couples the first and second leadframe elements together.

A packaged electronic device is disclosed, comprising: a package, a die and a first bondwire. The package comprises a leadframe. The leadframe comprises a first conducting leadframe element and a second conducting leadframe element that are separate from each other. The die comprises a first bondpad. The first bondwire electrically connects the first bondpad to the first conducting leadframe element. The die mechanically couples the first and second leadframe elements together.

Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.