The present disclosure relates to a semiconductor packaging method. The method includes: providing a first wafer; and performing a wafer stacking operation a plurality of times. The wafer stacking operation includes: forming a first to-be-bonded wafer in the shape of a boss, where the first to-be-bonded wafer includes a base and a protrusion from the base, and orientating the protrusion toward a second to-be-bonded wafer and bonding the protrusion to the second to-be-bonded wafer; forming a first dielectric layer on a surface of the protrusion; and performing second trimming on an edge region of the protrusion and an edge region of the second to-be-bonded wafer, so that the remainder of the second to-be-bonded wafer after the second trimming is in the shape of a boss, and using the remainder of the wafer stack after the second trimming as the first to-be-bonded wafer for next wafer stacking.

A die bonding apparatus includes: a mounting base including a mounting area on which a first member is mounted; a heater arranged below the mounting base; a side wall configured to surround the mounting area; a collet configured to hold a second member by vacuum-chucking at an end portion; a lid including a hole, the lid being mounted on the side wall; a moving structure configured to move the collet to transport the second member held by the collet through the hole for bonding the second member to the first member; and a gas-supplying tube arranged on the side wall and configured to supply a heating gas to a heating space formed by the side wall and the lid. The lid contains a material capable of: reflecting an infrared radiation caused by the heater and the heating gas; or absorbing and re-radiating the infrared radiation.

A power module includes a first conductor plate to which a first power semiconductor element is bonded, a second conductor plate to which a second power semiconductor element is bonded, the second conductor plate being disposed adjacent to the first conductor plate, a first heat-dissipating member disposed counter to the first conductor plate and the second conductor plate, and a first insulating sheet member disposed between the first heat-dissipating member and the first conductor plate. The first power semiconductor element is disposed at a position at which a first length from an end of the first conductor plate, the end being closer to the second conductor plate, to the first power semiconductor element is larger than a second length from an end of the first conductor plate, the end being far from the second conductor plate, to the first power semiconductor element, and the second length is larger than the thickness of the first conductor plate.

A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.

A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.

Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes dielectric layers, a conductive layer disposed in the dielectric layers, and a via layer disposed in the dielectric layers proximate the conductive layer. An underball metallization (UBM) layer is disposed in the dielectric layers proximate the via layer. A first connector coupling region is disposed in the via layer and the UBM layer. A via layer portion of the first connector coupling region is coupled to a first contact pad in the conductive layer. A second connector coupling region is disposed in the UBM layer. The second connector coupling region is coupled to a conductive segment in the UBM layer and the via layer. The second connector coupling region is coupled to a second contact pad in the conductive layer by the conductive segment.

The present disclosure relates to a semiconductor chip that allows electrical connections to be protected and a manufacturing method therefor.

A semiconductor chip has a strip-shaped region including a plurality of recesses on a side surface thereof. The recesses are arranged in a matrix of rows and columns on the side surface of the semiconductor chip or in a zig-zag pattern in the region. At least two of the strip-shaped regions are formed. The strip-shaped regions are formed in different positions between the vicinity of the center and opposed ends of the side surface. The strip-shaped region is partly inclined. The present disclosure can be applied for example to a semiconductor chip for a semiconductor device in which connections for electrically connecting the semiconductor chip and the substrate are protected with underfill.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises semiconductor chips stacked on a substrate and including first and second pads on top surfaces thereof, and bonding wires connecting the first and second pads to the substrate. The semiconductor chips alternately protrude in a first direction and its opposite direction. The semiconductor chip has a first lateral surface spaced apart from another semiconductor chip. The top surface of the semiconductor chip is provided thereon with a first arrangement line extending along the first lateral surface and with second arrangement lines extending from opposite ends of the first arrangement line. Wherein as a distance between the first and second arrangement lines increases, a distance between the second arrangement lines and the first lateral surface increases. The first pads are arranged along the first arrangement line. The second pads are arranged along the second arrangement lines.