A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure.

A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

A semiconductor device has a first board (10); and an intermediate layer (20) being provided on the first board (10) and having a plurality of connectors (31), (41). The first board (10) has a positioning section (5) that positions the intermediate layer (20). The intermediate layer (10) is provided with a positioning insertion section (37), (47), into which the positioning section (5) is inserted.

A method and apparatus are provided that includes an electronic device, a chip package and a method for cooling a chip package in an electronic device. In one example, the chip package includes an interposer or package substrate having a first IC die and a second IC die mounted thereon. The second IC die has a maximum safe operating temperature that is greater than a maximum safe operating temperature of the first IC die. An indicia is disposed on the chip package. The indicia designates an installation orientation of the interposer or package substrate which positions the first IC die upstream of the second IC die relative to a direction of cooling fluid flow.

An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the semiconductor chip pads and substrate pads include solder bumps. The solder bumps are deformed against the substrate pads and the semiconductor chip pads, whereby an underfill material is applied to fill the gap between the semiconductor chip and substrate. The underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads. At least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads, and at least another one of the solder bumps have been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads.

An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the semiconductor chip pads and substrate pads include solder bumps. The solder bumps are deformed against the substrate pads and the semiconductor chip pads, whereby an underfill material is applied to fill the gap between the semiconductor chip and substrate. The underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads. At least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads, and at least another one of the solder bumps have been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads.

A semiconductor device has a first board (10); and an intermediate layer (20) being provided on the first board (10) and having a plurality of connectors (31), (41). The first board (10) has a positioning section (5) that positions the intermediate layer (20). The intermediate layer (10) is provided with a positioning insertion section (37), (47), into which the positioning section (5) is inserted.

A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a semiconductor element mounted on the main surface of the substrate and having at least one element pad; a wire having a bonding portion bonded to the element pad; and a sealing resin formed on the main surface of the substrate for covering the wire and at least a portion of the semiconductor element. The semiconductor element has an element exposed side surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin.

An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure.